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Your system was fully tested at the factory. However, you can execute the tests to check if all is functioning as expected and get familiar with RT-LAB and your system.

Execute a Simple Functional Test and Demo

For a simple functional test of your system, you can execute one of the model examples provided as demos.
For example, you can load and execute the “rtdemo1” demo model, which is a PID controller. This model does not use the I/Os of your system.
If this model is running as expected, you know that your system basic configuration is correct.

The procedure is explained in this page of the RT-LAB user documentation: https://opal-rt.atlassian.net/wiki/x/MoiPC

Execute the Integration Test Model (Loopback Test)

We provide you the integration test model used to test your system in the factory.

Please, refer to this page in the RT-LAB user documentation for a detail: https://opal-rt.atlassian.net/wiki/x/_QiPC

The model includes the bitstream you should always use.

Download the integration test model file below on your PC.

  File Modified

What Is the Integration Test Model (Loopback Test)

The integration test model is a loopback model that outputs digital or analog signals from the simulator DB37 I/Os connectors to the digital or analog input DB37 I/Os connectors.
Signal readouts are viewed through the scopes of the MATLAB Simulink console of the model.

To validate the model, each output connector (digital or analog) should be physically connected to the corresponding input connector in order to read the signals received.
They can be connected all at once, or one at the time.

Use the Integration Test Model (Loopback Test)

Once the model downloaded, follow these instructions to use the model.
The main steps are described below. See this RT-LAB user documentation for details.
Also, don't forget to view our video tutorials RT-LAB - Real-Time Simulation Systems Fundamentals and register for your FREE online self-pace e-Learning courses.

  • Use the current workspace or use an existing workspace or create a new workspace in RT-LAB.

  • Import the integration test model in RT-LAB

    • Click File > Import

    • Select General > Existing Projects into Workspace

    • Choose Select archive file, then click the Browse button

    • Select the downloaded zip file and click Open, then click Finish

  • Build the integration test model

    • In the “HIL2GO_100_integration_test” tree, click Models.

    • Right click on IO_test and select Simulation > Build configurations…

      image-20241023-215039.png
    • Select your target (simulator) in the drop-down list “Development Node: on OPAL-RT (x64-based)

    • Click OK.

      image-20241101-154637.png

    • The model start building up. When done, the build log can be viewed under the Compilation tab in the bottom right panel.

    • Load the model.

    • Execute the model.

    • Use the MATLAB Simulink console to view signals and check if all the inputted signals corresponds to the outputted signals. See the following sections.

Connect the I/O cables

Use the loopback flat ribbon cable IDC40 to DB37M and the loopback board DB37, 40 positions with Vuser. See this page.

Before connecting the cables, make sure that the voltages or other electrical specifications are compatible with OPAL-RT DB37/DB9 specifications of I/O modules OP5330, OP5342 and, OP5369. See section HIL2GO-100 - OP4512 I/O System for all DB37 and DB9 pin assignment.

Refer to these pages for more details:

Din and Dout Loopback Test

  • Connect the loopback board to a Dout DB37 connector and connect the cable to a Din DB37

  • It is not mandatory to connect Vuser to a power source, but the Vuser Source switch must be set to “INT. 12V

  • Observe the Dout feedback on the Din using the integration model

    • See the examples below.

 🟢 EXAMPLE 1: Click to expand and view the PWM in example

PWM in - Pulse-width modulation digital in
Path to this view: IO_test/SC_Console/OP4512/GR1A DIN_DOUT (CH00-31)/PWMI CH08-15

image-20241031-151002.png
 🟢 EXAMPLE 2: Click to expand and view the TSD in example

TSD in - Time-Stamped Digital Input

Path to this view: IO_test/SC_Console/OP4512/GR1A DIN_DOUT (CH00-31)/TSDI CH00-07

image-20241031-155937.png
 🟢 EXAMPLE 3: Click to expand and view the QEIO Encoders example

QEIO Encoders (loopback slots 3A&B)
Quadrature Encoder Interface

Path to this view: IO_test/SC_Console/OP4512/GR3AB QEIO (00-01)
Note: Open the scope windows

image-20241031-164009.pngimage-20241031-163913.png

Ain and Aout Loopback Test

  • Connect the loopback board to an Aout DB37 connector and connect the cable to an Ain DB37

  • Observe the Aout feedback on the Ain using the integration model.

    • See the example below

 🟢 EXAMPLE: Click to expand and view the Analog In example

Analog in

Path to this view: IO_test/SC_Console/OP4512/GR2A AIN (CH00-15)
Note: Open the scope window of each input block by double-clicking on a block or via the right-click menu (showed below).

image-20241031-161259.png

Opening the scope windows for AINch0-7

image-20241031-161424.png
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