Description
The PWM Synchronize Ain functionality of the OPAL-RT Board driver provides the simulation with the possibility of outputting pulse width modulated (PWM) values through the digital output channels of the OP5354 or OP5360-2 modules installed on the simulator. These signals are then used to synchronize analog input signals going through the analog input channels of the OP5340 modules installed on the simulator.
In the case of the OP4200 chassis, the OP5360-2 used is incorporated into the I/O cassette with ID OP4260-1.
In order to generate valid PWM signals, only the duty cycle input is required. However, the Enable signal must be set at 1 to activate PWM generation. The shape of the PWM signals is defined by their frequency, phase, symmetricity and in the case of complementary signals, the dead time between them. There is also an option to set a delay between the model start time and the start of the PWM generation. These parameters are customizable for each PWM signal. A detailed description for them is given in the Signals Configuration section below.
The duty cycles must be between 0 and 1.
Usage
Once the bitstream configuration file has been parsed, the location of the digital output modules becomes visible to the user. The channels of the modules are in groups of eight. By clicking on each group, the user has access to the configurable options of the group.
Verifying that a bitstream has the PWM Synchronize AIn feature is done in the channel group configuration section. If the bitstream has this feature, the Digital type field is marked as Synchronize Analog and is displayed as a non-editable field (greyed out).
Channel Group Configuration
Enable | Checking this box enables the transmission of PWM data for the channels in the group once the simulation has started. Clicking Enable also adds the connection points for each of the 8 channels' Duty cycle and in the sensor view of Hypersim. |
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PWM period delay | This parameter specifies the time between the start of the CPU timestep and the start of the PWM period. |
Digital Type | In a case where the bitstream is PWM Synchronize AIn capable, this field is non-editable and is marked Synchronize Analog. |
Output Complementary | When this box is checked, a complementary signal will be generated for every other channel in the group, as seen in the schematic below:
Because a complementary signal is output on the channel adjacent to its reference, the number of user-configurable channels is divided by 2. Therefore, channels 1, 3, 5 and 7 in the signals list (where numbering starts from 0) will appear greyed out to denote that they will be used for outputting complementary signals. |
Signal Configuration
Channels in pulse width modulated output groups have the following parameters to configure:
Wave Mode | This parameter sets the generation pattern of the carrier wave of a signal. If the generation mode is set to Symmetric, the carrier is a triangular waveform. An Asymmetric generation mode corresponds to a sawtoothed carrier waveform.
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| Update Time | This parameter allows the user to choose the time the duty cycle of the PWM signal would be updated.
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Model period ratio | This parameter allows the user to set the frequency of the PWM signal. The frequency of the PWM signal is given by 1 / (Timestep * ModelRatio). Timestep is timestep of the CPU model and ModelRatio is the Model period ratio parameter |
| Phase (deg) | This parameter is used to specify the phase of the PWM signal. Accepted values for this field are any floating-point values between 0 and 360. |
Dead Time | This parameter is only visible if the Output complementary checkbox is selected. |
The inclusion of dead time reduces the length of the active phase of the two complementary waveforms, thus reducing their duty cycle. The value in this field denotes an amount of time (in us) during which the two complementary signals remain in their inactive phases. Accepted values for this field are any floating-point values between 20e-6 and 0.  | |
Characteristics and Limitations
For the connector pin assignments, the user should refer to the carrier documentation.
The current version of the pulse width modulated digital output functionality of the OPAL-RT Board driver has the following limitations:
- The duty cycle values must range between 0 and 1