Description
The current functionality is used to retrieve the raw data sent by an OPAL-RT card at each time-step. This is achieved by using the DataOUT ports of the FPGA.
It is meant for situations when the DataOUT ports are not directly connected to IO packing blocks.
The number of supported DataIN and DataOUT ports depends on the RT-XSG revision used to generate the bitstream. If it is revision 3.5.2 or above, bitstreams can have up to 64 DataIN input ports and 64 DataOUT output ports. Otherwise, they will have 32 DataIN input ports and 32 DataOUT output ports. Each port has a maximum width of 250 32-bit data words. These ports are used to exchange data between the HYPERSIM model and the FPGA chip of the card.
Note that knowledge of the bitstream logic generating the data sent through the DataOUT ports is necessary for a successful simulation.
Usage
Once the bitstream configuration file has been parsed, the ports capable of raw data transfer are revealed to the user.
If the bitstream offers the possibility of transferring raw data from the FPGA to the CPU then a new section named Data from board will appear as a subsection of the board's main configuration page. There, a dedicated configuration page will be created for each usable port, based on the information parsed from the bitstream configuration file. The title of each port's configuration page will contain the port number (count starting from 0) and the maximum number of DWORDS serviceable.
By clicking on a port's configuration page, the user will be able to create the data frame format expected from the FPGA. This can be achieved by adding, removing and/or moving signals up or down in the data frame table using the buttons found above the table. The configurable parameters of each signal are detailed in the section below.
Adding a signal to the data frame table will also make its connection point available in HYPERSIM.
If the table element has a vector size different from 1 (see section below for a description of the Vector size parameter), then its connectable item is an array.
For displaying and/or monitoring the data received from the FPGA, connections must be made between the points in the model and the raw data input connectable points.
Signal configuration
- Name
The name of the signal (or vector of signals) is important as it is the name given to the interface's connectable point. - Type
The type is selectable from a drop down list. The options are Bit, Unsigned, Signed, Float and Double. They represent the encoding to be used when interpreting data received from the FPGA.
If the Vector size is greater than 1, then this parameter will be applied to each element of the vector.
Certain types force other parameters to change their value to a fixed one:- The Bit encoding forces the Size (bits) parameter to 1
- Float forces the Size (bits) parameter to 32 and the Bit offset parameter to 0
- Double forces the Size (bits) parameter to 64 and the Bit offset parameter to 0
- Vector size
Setting this parameter different from 1 will result in the interface creating an array of signals starting at the byte offset specified. Each element of the vector will have the type, size, minimum and maximum values as specified in its table entry. The name of the connectable created for the vector will be the one specified at the parameter Name.
Using vectors can be beneficial when a data frame has contiguous signals that have the same parameters because it reduces the time necessary to configure the interface.
Keeping the value at 1 will maintain the current signal as an individual element of the data frame.
Current constraints are related to vector elements having to be aligned on byte-boundaries:- The Bit offset parameter cannot be different from 0
- The Size (bits) parameter must be one of the standard data type sizes (i.e. 1, 8, 16, 32 or 64)
- In the case of Type being set to Binary, the maximum vector size is 8
- Byte offset
This parameter represents the byte offset within the data port where the current table element will be read from.
Note that the interface has the means to check for data overlap: to check that the configuration is valid, the user must click on the Apply button of the I/O Interfaces Configuration window.
The current constraint is that on the OP4200 platform, the byte offset must be divisible by 4 when the signal is of type float and divisible by 8 when the signal is of type double. - Bit offset
This parameter represents the bit offset within the byte specified at the Byte offset parameter for the current table element.
Note that the interface has the means to check for data overlap: to check that the configuration is valid, the user must click on the Apply button of the I/O Interfaces Configuration window.
The Bit offset cannot be used (i.e. it is grayed out) for Float and Double signal types. It also can't be used in case the table element is a vector (i.e. Vector size is greater than 1). - Size (bits)
The Size (bits) parameter is where the size in bits of the current signal can be specified.
The size is fixed to 1 for Bit types, to 32 for Float types and to 64 for Double types. The maximum size allowed by the interface is 64 (which is the size of the largest native data type).
If the Vector size is greater than 1, then this parameter will be applied to each element of the vector.
Note that the interface has the means to check for data overlap: to check that the configuration is valid, the user must click on the Apply button of the I/O Interfaces Configuration window. - Min
The minimum value that will be reported in the HYPERSIM model for this signal. If the Vector size is greater than 1, then this parameter will be applied to each element of the vector.
Note that the value given by the FPGA could be lower than the minimum. In this case, the interface will report the minimum.
The value entered for this parameter is limited by the type and size of the signal. As an example, for an 8-bit signed signal, the minimum cannot be less than -128 (the smallest signed integer representable on 8 bits).
Furthermore, the value cannot be greater than the Max value (see item below).
The current limitation of this parameter is that it is not applicable for Float and Double types. - Max
The maximum value that will be reported in the HYPERSIM model for this signal. If the Vector size is greater than 1, then this parameter will be applied to each element of the vector.
Note that the value given by the FPGA could be greater than the maximum. In this case, the interface will report the maximum.
The value entered for this parameter is limited by the type and size of the signal. As an example, for an 8-bit signed signal, the maximum cannot be greater than 127 (the largest signed integer representable on 8 bits).
Furthermore, the value cannot be lower than the Min value (see item above).
The current limitation of this parameter is that it is not applicable for Float and Double types.
Characteristics and limitations
In order to correctly configure the data frames for each port, the user must have knowledge of how data on the ports of interest is generated by the logic implemented in the bitstream.
The current version of the raw data input functionality of the OPAL-RT Board driver has the following limitations:
- The bit offset must be 0 when the vector size is greater than 1
- The size (in bits) must be standard (i.e. 1, 8, 16, 32 or 64) when the vector size is greater than 1
- The maximum vector size is 8 for the binary data type
- On the OP4200 platform, the byte offset must be divisible by 4 for all signals of the type float
- On the OP4200 platform, the byte offset must be divisible by 8 for all signals of type double
- The bit offset cannot be used for any signals of type float or double (i.e. these types of data must be byte-aligned)
- The minimum and maximum parameters are not applicable for signals of type float
- The minimum and maximum parameters are not applicable for signals of type double