1xRing_14xADBMS6815_7820R

Specifications

Required Hardware

This configuration requires the following FPGA boards. Please refer to the linked product page for additional information.

Quantity	FPGA Board

Quantity	FPGA Board
1	PXIe-7820R

Modeling Capabilities

The pre-compiled FPGA firmware contains the following emulated devices arranged in a ring topology:

Ring ID	Device Type	Quantity of Devices

Ring ID	Device Type	Quantity of Devices
Ring 1	ADBMS6815	14

Signal Input and Output

The Digital IO channels available on the PXIe-7820R are configured to enable SPI communication between the emulated devices and an SPI master. The table below provides specification information for the channels as configured in the FPGA firmware. For a complete summary of specifications, please see the PXIe-7820R product page.

Standard SPI input and output signals are assigned to the DIO channels as described in the Pin Assignment table. Any DIO channels not listed in the table are inaccessible to the user.

Digital IO Channel Specifications

Digital IO Channel Specifications
Maximum Frequency	80MHz
Digital Logic Family	3.3V TTL
LOW Input Voltage Range	-0.3V to 0.80V
HIGH Input Voltage Range	2.00V to 3.6V

Pinout Diagram for each connector of the PXIe-7820R.

Pin Assignment

Connector	Pin Name	Pin Number	Signal Name	Direction

Connector	Pin Name	Pin Number	Signal Name	Direction
Connector 0	DIO0	65	SCK Port A	Input
Connector 0	DIO1	31	CS Port A	Input
Connector 0	DIO2	63	MISO Port A	Output
Connector 0	DIO3	29	MOSI Port A	Input
Connector 0	DIO4	61	SCK Port B	Input
Connector 0	DIO5	27	CS Port B	Input
Connector 0	DIO6	59	MISO Port B	Output
Connector 0	DIO7	25	MOSI Port B	Input
Connector 0	DIO8	57	SCK Port U	Output
Connector 0	DIO9	23	CS Port U	Output
Connector 0	DIO10	55	MISO Port U	Input
Connector 0	DIO11	21	MOSI Port U	Output
Connector 0	DIO12	53	SCK Port D	Output
Connector 0	DIO13	19	CS Port D	Output
Connector 0	DIO14	51	MISO Port D	Input
Connector 0	DIO15	17	MOSI Port D	Output