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Examples | Static Synchronous Series Compensator (SSSC)


A Static Synchronous Series Capacitor (SSSC) is connected in series between bus B1 and B2, which controls the injected voltage amplitude, while keeping it in quadrature with the line current. The series converter consists of a 100 MVA, three-level, 48 pulse neutral point clamped (NPC) based converter. It can inject a maximum of 10% of the nominal line-to-ground voltage (28.87 kV) in series with line L2.


This example model can be found in the software under the category FACTS & HVDC with the file name SSSC.ecf.

Simulation and Results

In the model, make sure that the value of the Td=0.3 s and Ton= 0.8 s in the pulse delay and extended ON time block. The gain block, which comes after the delay block, should be set to V_ref =0.08 pu. This means that the initial voltage is set to 0 pu, then at t=0.3 sec it will ramp to 0.08 pu. To synchronize the applied reference with the ScopeView data acquisition, the SyncOut from the point of wave synchronization is being used.

Run the simulation and observe on the ScopeView template the impact of the injected voltage on the P and Q flowing in the 3 transmission lines. Also, observe the waveforms of the injected voltage and the current flowing through the SSSC voltage and current stay in quadrature so that the SSSC operates as a variable inductance or capacitance.


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