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RT Monitor

The RT Monitor Tool allows the user to keep track of the simulation performance.


Introduction

Every time step is separated in several actions for which the exact timing can be monitored in real-time. This is especially useful for optimization or debugging purposes.

The tab is separated into 2 sections:

  • The left section with Hardware resources

  • The right section with CPU Monitoring

Hardware Usage Information

Since multiple users can access the same target simulator, it's important to keep track of who is using what resources. 

  1. Displays the matrix of cores affinity. Useful only with large models running on PC clusters where the distance between two cores can have a perceptible effect on performance.

  2. Reserves cores in advance for a single user or liberates cores after use.

  3. Forces liberation of a core in use by another user.

  4. Expands or collapses the information tree in (7).

  5. Refreshes usage information.

  6. Filters the list of cores in (7).

  7. List of licensed cores and information about their specifications and usage.

CPU Monitoring

Monitor in real-time the performance of all the cores used by the simulation and help answer these questions: Are there overruns or stretched steps? How big is the real execution time? How much idle time is available? 

  1. Select all or no core to monitor.

  2. Toggle which categories of values are to be monitored.

  3. Run a single acquisition, or start continuous monitoring.

  4. Reset the Timing or Performance values.

  5. Monitored values per core. 

  6. Add/Remove values from the table. See the full list below

All times displayed in the Performance Monitoring tab are in microseconds.

The max and min values are common to all CPUs reserved by HYPERSIM. In addition, the stretched steps value is incremented in a unique CPU task, the main task.

Below is the list of available values:

Select

Uncheck to disable monitoring on the corresponding core

Id

Core number

Enabled

Core state

Exec

The execution time of simulation tasks during the monitored time step

Exec Max

The maximum execution time of simulation tasks, since monitoring start or last reset

Remain

Remaining idle time after all actions have been executed and before the next step, sum of waiting and synchronization times

Remain Min

Minimum remaining idle time, since monitoring start or last reset

Comm

Time used for communication between cores

Comm Min

Minimum time used for communication between cores since monitoring start or last reset

Comm Max

Maximum time used for communication between cores since monitoring start or last reset

Sync

Time spent in the inter-core synchronization barrier

Sync Min

Minimum synchronization time, since monitoring start or last reset

Sync Max

Maximum synchronization time, since monitoring start or last reset

Wait

Time waiting for real-time synchronization

Wait Min

Minimum wait time, since monitoring start or last reset

Wait Max

Maximum wait time, since monitoring start or last reset

Sim

Complete simulation time step measurement

Sim Min

The minimum duration of the time step, since monitoring start or last reset

Sim Max

The maximum duration of the time step, since monitoring start or last reset

Acq/Par

Simulation server request handling time (e.g. signal acquisition and parameter change)

Acq/Par Max

Maximum simulation server request handling time, since monitoring start or last reset

IO Out

Outbound I/O service time (analog, digital and various communication protocols)

IO Out Max

Maximum I/O outbound service time, since monitoring start or last reset

IO In

Inbound I/O service time (analog, digital and various communication protocols)

IO In Max

Maximum I/O inbound service time, since monitoring start or last reset

Missed I/O Adp1

Legacy. Number of steps where I/O adapter 1 could not service I/Os properly, since simulation start or last reset

Missed I/O Adp2

Legacy. Number of steps where I/O adapter 2 could not service I/Os properly, since simulation start or last reset

Last in Sync

The number of times the core arrived last in the synchronization barrier, since simulation start or last reset. The master core always arrives last under normal operation.

Stretched Step

The number of steps where execution delays could not be compensated in the following step, since simulation start or last reset.

Below is a diagram showing each of the timings measured during the simulation, at each time step:



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