Open

Requirements

The RT-LAB, Schematic Editor and eFPGASIM toolboxes must be installed on the host and target computers in order to run this example model properly. Please refer to the product documentation for details on version compatibility.

Setup and Connections

This model must be run with both the Hardware Synchronized and XHP modes enabled. The firmware used in this model is generated using the RT-XSG tool, and it can be modified to generate firmware to fit another I/O hardware configuration. The CPU model simulation time step is set to 20 microseconds and all the variables required for controller is defined in the "ParameterInitialization.m" file that is automatically loaded during simulation.

• DB37 pin-based digital loop-back cable must be connected at the rear side of the simulator to transfer the gating pulses.

Open

Procedure

RT-LAB model with eHS interface

The following procedure will help the user understand the functionality and linking between eFPGASIM, RT-LAB and Schematic Editor. A Hardware-in-the-loop based RT-LAB model, "SCIM_SFUN_rtlab_SE_IO", is provided to illustrate the exchange of information between the controller and plant.

1. Click on "Run this demo" at the top of this section. The RT-LAB model will open automatically.

2. The RT-LAB model consists of a master subsystem (i.e. "sm_computation") and a console subsystem (i.e. "sc_user_interface").

   • The master subsystem has power network interface ("eHS_SE_SFunction_Drivers") and control of the machine

• The console subsystem is used to control set points, such as magnitude and frequency of source voltages, speed reference, mechanical torque, and control activation during real-time simulation. Users can also monitor voltages, currents, machine torque and speed of the machine at any point during the simulation.

3. The "eHS_SE_SFunction_Drivers" solver solves the power network built using schematic editor software during the real time simulation. The circuit built in schematic editor can be edited or viewed by choosing the edit option available in the solver block.

4. eFPGASIM allows to simulate two different models for the squirrel cage induction machine:

   • linear (or unsaturated) induction machine;

   • saturated induction machine.

   In the linear machine model the effects of magnetic saturation are neglected, in contrast with the induction machine with saturation, where these effects are taken into account. Each model has its own block in OPAL-RT Schematic Editor Library Browser, with different parameters to be set, as shown in the figures below.

This example provides two RT-LAB projects, each containing one of these machine models, and their results are presented in a following section.

5. When the model is compiled in Simulink, the configuration of the eHS solver will be generated according to the schematic editor circuit characteristics. Elements will be put into matrices and stored in .mat files that will be transferred into the solver when the model is run from the RT-LAB interface. Matrices are generated during model compilation in RT-LAB.

6. Field Oriented Control of SCIM is implemented on the CPU which runs at a sampling time of 20 micro-sec. This has a standard outer loop speed control and inner loop current control implemented. The transformation used is original parks transformation (2/3 factor) with d axis aligned to phase A axis. The modulating waves are clamped to a value between 0 and 1 using a clamping circuit. The carrier frequency is 10000Hz. Exchange of information between the controller and plant happens within the software model. Machine generated currents, speed and theta information are routed to the controller as an input, and output of the controller is send out by mapping frequency and duty to digital out configuration through OpOutput.

7. Modulating waveforms generated by the controller are converterd to PWM via pwmo IO block of OPAL-RT. These pwm pulses are fed back through digital loop-back cable to fire the eHS converter internally. Here, the gating pulses are chosen to receive from Digital In card of the OPAL-RT simulator. Here, to receive the pwm in schematic editor, slot 2A channels 00 to 05 are configured.

8. The OPAL-RT hardware chasis and FPGA module has to be chosen in the schematic editor prior to the building of the model. Goto: File - Simulator Setup - Choose the Simulator - Choose the Firmware. Mark the "Use this setup" to fit your simulation requirement.

9. During real-time execution;

   1. To set the reference speed: Give value between 0 and 100 to Speed_Ref;

   2. To add mechanical torque to the machine: Give value between 0 and 50 to Mech_Torque.

   3. To start the control algorithm: Give value 1 to PWM_Enable.