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v2.15 Boost and Two Level Inverter - S-Function

Description


This project demonstrates the use of the eHS solver to compute the outputs of an FPGA-based Boost and Two-Level Inverter circuit in real time. The FPGA-based circuit comprises of a boost converter followed by a two-level DC/AC converter with fault insertion Ton the third phase. This circuit is created using the OPAL-RT Schematic Editor. With this example project, the user is able to control the simulation parameters (inputs and gates values) in real-time via the RT-LAB console.

In S-Function workflow, example models support any chassis. You can contextualize your example model by selecting the chassis in the Chassis selection block.

SCHEMATIC EDITOR S-function OP4510 OP4512 OP4610 OP5607 OP5707

Table of Contents

Requirements


RT-LAB, the SimPowerSystems Simulink toolbox, and the eHS Power Electronics Toolbox must be installed in order to successfully run this example project.

This project uses an external Digital Out to Digital In loopback connection to control the gates. Connect a loopback cable from digital output to digital input on the simulator. This is essential to successfully run the simulation.

Setup Parameters


The following parameters used for real-time simulation are editable by the user inside the Boost_and_2LvlInverter_param.m file found in the model directory:

  • Ts: CPU Simulation time step - the default is 20µs.

  • Boost_Vin: Voltage input of the boost converter

  • Boost_PWM_Freq: Carrier frequency of the boost PWM generator

  • Boost_PWM_Duty: Duty Cycle of the boost PWM generator

  • Inv_PWM_CarrierFreq: Carrier frequency of the two-level PWM generator

  • Inv_PWM_ModulationIndex: Modulation index of the two-level PWM generator

  • Inv_PWM_ShiftAngle: Shift angle between the BEMF generator and the PWM/Vabc setpoints generator

  • Inv_PWM_Out: AC base frequency of the two-level inverter

  • Inv_BEMF_Ampl: Amplitude of the BEMF

Real-Time model


The RT model is composed of the following two main subsystems: the Console (SC) and the Master (SM).

  • The console subsystem, which runs on the host computer, manages the communication between the host computer and the target simulator. It is used as a user interface during the real time simulation to control the model and visualize the outputs of the eHS solver.

  • The master subsystem, which runs in real time on the target simulator, manages the communication between the CPU model and the eHS solver running on the FPGA. For example, the carrier frequency, output frequency, and modulation index parameters sent from the console are processed in the Circuit_Control subsystem into frequency and duty cycle control values, which are subsequently sent as a PWM signal to the Digital-Out.

  • There are two ways to configure IO block. One is using OPAL-RT Board drivers while the other is configured with S-Function drivers. Since eFPGASIM 2.9, it's possible to use eHS with Schematic Editor plus S-Function drivers.

 

Running the model


In order to run the example, follow the procedure below:

  1. If you have eFPGASIM installed, add the example project to RT-LAB by selecting File>>New>>RT-LAB Project>>eFPGASim>>Schematic_Editor_Workflow>>eHS Gen 4>>Boost_and_Two_Level_Inverter>>SFUN.

  1. Compile the RT Model by clicking on Build in RT-LAB.

  2. Once the model has been successfully built, Load and Execute the model in RT-LAB in order to begin the real-time simulation.

  3. Once the real-time model and the eHS are running, observe the results of the eHS simulation by opening the Scope blocks in the Simulink Console.

  4. Modify the parameters of the circuit from the Simulink Console and observe their effects on the Scopes. For instance, to produce an open-phase fault on the A phase of the two-level inverter, set the constant of the fault to 0.

 

 

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