Open

Requirements

RT-LAB, the SimPowerSystems Simulink toolbox, and the eHS toolbox must be installed in order to successfully run this example project.

This project uses an external Digital Out to Digital In loopback connection to control the gates. Connect a loopback cable from DO to DI on the simulator. This is essential to successfully run the simulation.

Open

Setup Parameters

The following parameters used for real-time simulation are editable by the user inside the init_PFC_Boost_HB_LLC.m file found in the model directory:

• Tsc: CPU Simulation Time Step - the default is 10µs.

• Line_Voltage_Peak: Input Voltage Peak to the Full Bridge Rectifier

• BVoref: Desired Output Voltage from PFC Preconverter

• Power: Maximum Steady State Power Capability

• del_V: Peak-Peak Output Voltage Ripple

• IndCurrRipple: Inductor Current Ripple

• Conv_efficiency: Nominal Efficiency of the Converter

• t_holdup: Minimum hold up time for a Minimum Output Voltage

• f_sw: MOSFET Switching Frequency

• llc_frequency: LLC Switching Frequency

• llc_duty: LLC Switching Duty

As the current flowing through the inductor is never zero during the switching cycle, the boost converter operates in Continuous Conduction Mode (CCM). The inductor current and the output voltage profiles are controlled using simple integral control. During start up, the reference output voltage is ramped up to the desired voltage.

The LLC converter is a DC/DC converter based on a resonant circuit which allows soft-switching operation. The LLC resonant circuit reduces switching loss through zero-voltage switching (ZVS). Unlike the SLR converter, the LLC converter can keep the output voltage regulated even under light load condition. The converter consists of a switching bridge (half-bridge MOSFET), an LLC resonant circuit, a full-bridge rectifier and an output filter (Co). The resonant circuit consists of the primary leakage inductance of a transformer (Llkp), its secondary leakage inductance (Llks), its magnetization inductance (Lm) and a capacitor Cr.

Real-Time model

The RT model is composed of the following two main subsystems: the Console (SC) and the Master (SM).

• The console subsystem, which runs on the host computer, manages the communication between the host computer and the target simulator. It is used as a user interface during the real time simulation to control the model and visualize the outputs of the eHS solver.

• The master subsystem, which runs in real time on the target simulator, manages the communication between the CPU model and the eHS solver running on the FPGA. For example, the pfc frequency, llc frequency, and llc duty are sent from the console are processed in the pfc control block into frequency and duty cycle control values, which are subsequently sent as a PWM signal to the Digital-Out.

Running the model

In order to run the example, follow the procedure below:

1. If you have eFPGASim installed, add the example project to RT-LAB by selecting File>>New>>RT-LAB Project>>eFPGASim>>OPAL-RT Schematic Editor>>OP5607>>Boost_and_TwoLevel_Inverter.

2. Compile the RT Model by clicking on Build in RT-LAB.

3. Once the model has been successfully built, Load and Execute the model in RT-LAB in order to begin the real-time simulation.

4. Once the real-time model and the eHS are running, observe the results of the eHS simulation by opening the Scope blocks in the Simulink Console.