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v2.15 PMSM dQ Field Oriented Control - S-Function
Description
This model illustrates the closed-loop control of a Permanent Magnet Synchronous Machine (PMSM), connected to a two-level voltage source converter developed in schematic editor software and solved using the eHS solver. This example is based on OPAL-RT's real-time simulator, which has CPU and FPGA as two major processing units: the PMSM and the converter are simulated on FPGA and the controller is simulated on CPU in real-time. One RT-LAB model and one schematic editor model is provided to illustrate the exchange of information between the controller and plant
In S-Function workflow, example models support any chassis. You can contextualize your example model by selecting the chassis in the Chassis selection block.
SCHEMATIC EDITOR S-function OP4510 OP4512 OP4610 OP5607 OP5707
Requirements
The RT-LAB, Schematic Editor and eFPGASIM toolboxes must be installed on the host and target computers in order to run this example model properly. Please refer to the product documentation for details on version compatibility.
Setup Parameters
This model must be run with both the Hardware Synchronized and XHP modes enabled. The firmware used in this model is generated using the RT-XSG tool, and it can be modified to generate firmware to fit another I/O hardware configuration. The CPU model simulation time step is set to 25 microseconds and all the variables required for controller is defined in the "ParameterInitialization.m" file that is automatically loaded during simulation.
DB37 pin-based digital loop-back cable must be connected at the rear side of the simulator to transfer the gating pulses.
Procedure
RT-LAB model with eHS interface
Run this demo : efsOpenExample('PMSM_SFUN_SE_rtlab_IO');
The following procedure will help the user understand the functionality and linking between eFPGASIM, RT-LAB and Schematic Editor. A Hardware-in-the-loop based RT-LAB model, "PMSM_SFUN_SE_rtlab_IO", is provided to illustrate the exchange of information between the controller and plant.
Click on "Run this demo" at the top of this section. The RT-LAB model will open automatically.
The RT-LAB model consists of a master subsystem (i.e. "sm_computation") and a console subsystem (i.e. "sc_user_interface").
The master subsystem has power network interface ("eHS1") and field-oriented control of the machine
The console subsystem is used to control set points, such as magnitude and frequency of source voltages, speed reference, mechanical torque, and control activation during real-time simulation. Users can also monitor voltages, currents, machine torque and speed of the machine at any point during the simulation
The "eHS1" solver solves the power network built using schematic editor software during the real time simulation. The circuit built in schematic editor can be edited or viewed by choosing the edit option available in the solver block.
When the model is compiled in Simulink, the configuration of the eHS solver will be generated according to the schematic editor circuit characteristics. Elements will be put into matrices and stored in .mat files that will be transferred into the solver when the model is run from the RT-LAB interface. Matrices are generated during model compilation in RT-LAB.
Field Oriented Control of PMSM is implemented on the CPU, which runs at a sampling time of 25 microseconds. This has a standard outer loop speed control and inner loop current control implemented. The transformation used is quadrature transformation with d axis aligned to phase A axis (Original Park). The modulating waves are clamped to a value between 0 and 1 using a clamping circuit. Exchange of information between the controller and plant happens within the software model. Machine generated currents, speed and theta information are routed to the controller as an input.
Modulating waveforms generated by the controller are converterd to PWM via pwmo IO block of OPAL-RT. These pwm pulses are fed back through digital loop-back cable to fire the eHS converter internally. Here, the gating pulses are chosen to receive from Digital In card of the OPAL-RT simulator. Here, to receive the pwm in schematic editor, pin DI33 to DI38 are configured.
The measurements in the schematic editor FPGA model can be configured to route them via DAC with necessary settings. Similarly, the inputs can be received from either CPU or by configuring the ADC's of the real time system. User can opt to read the measurements to the cpu environment or configure IO's to interface external hardware. Similiarly, few parameters are given access to define in the schematic itself or from the CPU model.
The OPAL-RT hardware chasis and FPGA module has to be chosen in the schematic editor prior to the building of the model. Goto: File - Simulator Setup - Choose the Simulator - Choose the Firmware. Mark the "Use this setup" to fit your simulation requirement.
During real-time execution;
Speed reference is set to 1000rpm. It can be varied unitl 1500rpm
Load Torque is 2 by default. Machine can handle 10N-m load torque
By default, Torque input is provided to the machine. To use speed as an input to the machine, provide '0' to the Mode.
The figure shows the variation of electromagnetic torque, currents drawn, and the shaft speed of PMSM with the addition of a mechanical load.
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