Description

This block contains the eHS Gen4 Solver core, a powerful floating-point solver, which enables the user to simulate a power electronics circuit on FPGA automatically without having to program the mathematical equations. This block solves the current and voltages within the circuit on an Opal-RT FPGA based simulator with sample times below 1µs.

This FPGA block requires the use of the "eHS Gen4 Unpacking" block which is contained inside the efs_packing_lib. Moreover in order to use the solver, the stream which contains the configuration data needs to be sent from the CPU model by the eHS Gen4 CommBlk.

Mask Parameters

eHS Solver form factor: This option selects the solver computational unit form factor.

Provide external SW input port for control from digital inputs: When this option is selected, an input will be provided for feeding the eHS solver with explicit gating signals originating from digital inputs.

Provide external SW input port for control from PWM generators: When this option is selected, an input will be provided for feeding the eHS solver with explicit gating signals originating from RT-XSG-based Pulse-Width-Modulation (PWM) generators [PWMO blocks].

Provide external SW input port for control from TSDO generators: When this option is selected, an input will be provided for feeding the eHS solver with explicit gating signals originating from RT-XSG-based Time-stamped Digital Output (TSDO) generators [TSDO blocks].

Provide external SW input port for control from static switches: When this option is selected, an input will be provided for feeding the eHS solver with explicit gating signals originating from RT-LAB-based static switches. [Digital Out blocks].

Provide external U input port for source from a rescaled analog input: When this option is selected, an input will be provided for feeding the eHS solver with source input signals originating from analog inputs (rescaled by an Analog Input Differential Rescaling Block).

Provide extra External U input: This option allows to use up to 5 extra FLWS inputs to connect the eHS to external sources or models.

Provide low latency output port: When this option is selected, an output port is added to the eHS block to add the low latency output port to the block.

Inputs

Config

From CPU: This input should be connected to the DataIN and LoadIN blocks through an eHS Gen4 Unpacking block. It receives all necessary info from the RT-LAB model.

Switches

External SW (DIn): If this option is selected in the CPU block, this port enables the use of explicit gating signals coming from digital inputs by eHS. The effective number of bits of this input depends upon the solver form factor. Consult the table below for the expected data types depending on the solver form-factor.

External SW (Static): If this option is selected in the CPU block, this port enables the use of explicit gating signals coming from static swtiches by eHS. The effective number of bits of this input depends upon the solver form factor. Consult the table below for the expected data types depending on the solver form-factor.

External SW (PWM): If this option is selected in the CPU block, this port enables the use of explicit gating signals generated inside the FPGA by eHS. The effective number of bits of this input depends upon the solver form factor. Consult the table below for the expected data types depending on the solver form-factor.

External SW (TSDO): If this option is selected in the CPU block, this port enables the use of explicit gating signals generated inside the FPGA by eHS. The effective number of bits of this input depends upon the solver form factor. Consult the table below for the expected data types depending on the solver form-factor.

The table below lists the supported data types for various inputs:

Inputs (OPAL-RT FLWS protocol)

External U (AIn): If this option is selected in the CPU block, this port enables the use of rescaled analog inputs as sources to the eHS. It should be connected to the serial output of an Analog Input Differential Rescaling Block. This signal should follow the OPAL-RT FLWS protocol.

Extra U (1 to 5): If this option is selected in the CPU block, this port enables the use of an output originating from another eHS core to control a current or voltage source within the solver. This signal should follow the OPAL-RT FLWS protocol.

Outputs

Outputs : This output port provides FLWS bus that streams the eHS outputs for use in the RT-XSG model. It is provided as a Bus following the OPAL-RT FLWS protocol.

Low latency outputs: This output port provides a FLWS bus that streams the eHS low latency outputs. The low latency outputs of the eHS are provided to couple external models in order to optimize the coupling latency and enhance the stability of the model decoupling.

If you require more information, please contact https://www.opal-rt.com/contact-technical-support/.