Description

This block allows the configuration and the control of an eHSx32 Gen3 solver to compute the outputs of a power-electronic circuit on an OP4200 target. The eHS Gen3 core is located on an FPGA-based board and runs at higher sample rate that the RT-LAB system.

The netlist file can be either a Simscape Electrical Specialized Power Systems (SPS) Simulink model (.mdl), a PLECS Simulink model (.mdl), a PSIM netlist (.psimsch), or an NI Multisim netlist (.xml). The block enables the real-time control of its voltage and current sources as well as the gated signals of the switches.

Mask Parameters

Circuit Tab

The Circuit Tab allows the user to load a Circuit model to the eHS block, to configure the Timestep of the FPGA simulation, and to view information about the Circuit model.

Circuit: Allows the user to select the file describing the circuit intended to be simulated using eHS. This file should be created with one of the supported circuit editors detailed in the Description above. See the User Guide, Quickstart Guide, and example project for details on how to design this circuit for use with the eHS.

Timestep: Details the Timestep in seconds used to simulate the circuit described in the Circuit which will be run on the FPGA target. By default, the timestep is set to the minimum value. The minimum solver sample time depends on the complexity of the circuit, and typically ranges in the hundreds of nanoseconds. By deselecting Auto, the user can specify their own timestep in the range of 160ns to 2us.

This option may be useful for:

• Accelerating the offline simulation, where the step size has to be set to the greatest common divisor of the eHS step size and the real-time (RT-LAB) system step size (down to 5 ns without setting an explicit sample time)
• Testing different sample times
• Reducing the quantization error for systems that contain very large time constants (>> 10sec)
• Synchronizing the eHS with another FPGA solver core

Circuit Info: Details useful information about the circuit file chosen, including the number of Voltage and Current Sources (Input), the number of Switches (Gates), the number of Measurements (Outputs), and the number of States to be computed (NSD).

Gates Tab

The Gates Tab allows the user to view information about the switches extracted from the Circuit model and allows for configuration of the Switch Source Type, Channel, Polarity, and Switch Conductance (Gs) values. Each row of the table represents a different switch in the Circuit model.

Name: Describes the name of the switch used in the Circuit model, from the top-level of the model (i.e. including subsystems). If a component used in the Circuit model contains more than one switch, it will be split into multiple rows, with an _index attached.

Type: Describes the type of the switch used in the Circuit model. For more information on what blocks are supported in the different circuit editors, please see the User Guide.

Source Type: Allows the user to select which source type is used to drive the switch. The current options are from the I/O via the DIN or via the CPU, where CPU is the default value. Diodes are always shown as UNCONNECTED as they do not accept gated signals.

Note: Each switch defined as having a Source Type of CPU will create an input port to the eHSx32 for OP4200 block, allowing the user to wire an input from the CPU model to the eHS.

Channel: Allows the user to select which source channel is used by the switch. The range of possible values is determined by the bitstream configuration file and begins at 1. For example, if the user would like to map one of their IGBT-Diodes to the first Digital In I/O channel, the user should select DIN as the Source Type and 1 as the Channel. The default value of the Channel is an increment above the previous row's channel value. Also, Diodes are always shown as having a -2 channel as they do not accept gated signals.

Note: When selecting CPU as a Source Type, ensure that the Channels for the CPU rows are in ascending order, each value being an increment of one compared to the value in the previous CPU row.

Polarity: Allows the user to select the polarity of the simulated switches to be active-high (HIGH) or active-low (LOW). The default value of the Polarity is HIGH. Diodes are always shown as having a polarity of NONE as they do not accept gated signals.

Gs: The conductance of the switches of the circuit. When using the two-level or three-level LCA, all switches in the component must have the same Gs values defined.

To open the eHS Optimization Tool for more information on this parameter, type GsGui2 into the MATLAB Command Window.

Inputs Tab

The Inputs Tab allows the user to view information about the Voltage and Current Sources extracted from the Circuit model and allows for configuration of the Signal Source and Parameters of each source. Each row of the table represents a different source in the Circuit model.

Name: Describes the name of the sources used in the Circuit model, from the top-level of the model (i.e. including subsystems).

Source Type: Allows the user to view whether the source is a Voltage or Current source.

Signal Source: Allows the user to select the Signal Source of the Circuit model Voltage or Current Source. The possible options are to route a value via the CPU or to route a Constant. If the user selects CPU, the block will expose a port for routing the signal to the eHS block. If the user selects Constant, the Parameters panel will expose a Constant Value text box, allowing the user to enter a constant value. The default setting for the Signal Source is CPU.

Outputs Tab

The Outputs Tab allows the user to view information about the Voltage and Current Measurements extracted by the Circuit model. Each row of the table represents a different Measurement in the Circuit model. The order of the outputs described in this table represents the order of elements in the Average and Downsample vector outputs of the eHSx32 for OP4200 block.

eHS Output Name: Describes the name of the eHS outputs returned by the eHS block.

Circuit Measurement Names: Describes the name of the Measurement as described in the Circuit model, from the top-level of the model (i.e. including subsystems).

Measurement Type: Describes the Measurement type, between Voltage or Current of the measurements as described in the Circuit model.

Log Tab

The Log Tab allows the user to view debugging information about the Circuit model loading, parsing, and extraction process. In case of any issues encountered during these steps, an error, warning, or message is generated and logged in the Log Tab. The following standard is applied:

• Errors are logged in red.
• Warnings are logged in yellow.

Inputs

Any input or gate configured to be mapped to a CPU source will generate an entry port to the eHSx32 for OP4200 block. These inputs will be sampled at the CPU Timestep defined in RT-LAB.

Note: The block currently does not support the RTE data type as a source to gates. The block also does not support inputs sourced from Bus Selector blocks, but a Gain function can be added between the Bus Selector and the input to the eHS to work around this limitation.

Outputs

Average: A vector of average eHS output values, each element representing an average over the CPU Timestep for each eHS output (i.e. for eHS_Y1, all values computed by the FPGA-based eHS solver over one CPU timestep for eHS_Y1 are averaged over one CPU timestep). The width of the vector is equal to the number of measurements in the block. Please refer to the 22920834 section for more information on the order of these outputs.

Downsample: A vector of decimated eHS output values, each element representing the latest value within one CPU timestep of each eHS output. Please refer to the 22920834 section for more information on the order of these outputs.

Characteristics and limitations

Number of elements: Please refer to the eHS User Guide for more detail of this block's Specifications.

• The maximum number of inputs (Current or Voltage Sources) in the circuit is 32 elements.
• The maximum number of switching devices (IGBT/Diode, Diode, Ideal Switch, or Breaker) in the circuit is 48 elements.
• The maximum number of outputs (Current or Voltage Measurements) in the circuit is 32 elements.
• There is no limitation on the number of resistors.
• The solver time step is limited to approximately 2.31us.
• Inductors and capacitors can be used as much as necessary as long as the time step do not cross the limit of approximately 2.31us. Please note that the use of Inductors, Capacitors and Switches has a strong impact on the minimum achievable time step, whereas Inputs and Outputs have a smaller effect.

Circuit design: Please refer to the eHS User Guide and example models for details on how to design the circuit for use with the eHS.

Offline simulation: This block does not directly support offline simulation. For offline simulation, refer to the eHS Offline Simulation block in the eFPGASIM >> eHS and Converter Models >> Tools Simulink Library. This block enables the developer to connect the block exactly as it is connected inside the FPGA (e.g. to a plant model) for more accurate results.

Additional Support Comments:

• This block does not currently support the eHS Scenarios feature or RT-EVENTS.
• For more details on how to use this block in the RT-LAB workflow with the OPAL-RT Boards User Interface, please refer to the QuickStart Guide.

If you require more information, please contact https://www.opal-rt.com/contact-technical-support/.