Description

Opal-RT eHS - electric Hardware Solver - is a powerful floating-point solver OPAL-RT is developing that enables the user to simulate an electric circuit on FPGA automatically without having to write the mathematical equations. It merges the simplicity of building electric circuits models with the Simscape Electrical Specialized Power Systems (SPS) Toolbox with the strength of Opal-RT FPGA-based simulators to solve the currents and voltages within the circuit in real-time with a sample time below 1us.

This block implements a generic eHS solver inside a RT-XSG model describing the firmware of the FPGA board.

Mask Parameters

Provide external U input port: When this option is selected, an input will be provided for feeding the eHS solver with explicit inputs. Otherwise, only the inputs provided by the CPU model are used.

Provide external C input port: When this option is selected, an input will be provided for feeding the eHS solver with explicit gating signals. Otherwise, only the gating signals provided by the CPU model are used.

Inputs

eHS param and CPU inputs: This input should be connected to the DataIN and LoadIN blocks through an "Dual eHS unpacking" block. It receives all necessary info from the RT-LAB model.

External U: If this option is selected in the CPU block, this port enables the use of explicit input signals generated inside the FPGA by eHS. It should be a bus of sixteen XFloat8_24 signals.

External C: If this option is selected in the CPU block, this port enables the use of explicit gating signals generated inside the FPGA by eHS. It should be a UFix24_0 signal.

Outputs

Y: This output is a vector, each element being one of the outputs of the eHS solver. The bus is composed of sixteen Xfloat8_24 signals.

Characteristics and limitations

This block has no special characteristics.

If you require more information, please contact https://www.opal-rt.com/contact-technical-support/.