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The OP7817 (also named OP7817-2) provides 16 push-pull digital output signals with specific voltage conditioning. All outputs are updated individually by the OP7000 or OP7000V2 Primary FPGA with a maximum time delay of fewer than 75 nanoseconds.

All outputs support voltages up to 30V and the output current is up to 100mA in push-pull.

The board also holds a CPLD which allows controlling the line states when the Primary FPGA is inactive, such as during the power-up phase of the chassis.

Board Layout

The 16 channels are routed via the mid-plane of the chassis to the Primary FPGA card (OP7161-1 or OP7170-1) which controls the channels' state.  

Open

Output Circuit Description

The diagram below illustrates the circuit for one channel. The state of the Vout output is controlled by the FPGA, and its value depends on the V_User and V_User_RTN values.

Open

On the actual board, the circuitry uses dual opto-coupler and operational amplifiers for consecutive channels (channels 0 and 1, 2 and 3, etc.).

Electrical Specifications

The measurements provided below are for typical Vuser values, but the board can also operate between the specified ranges.

*Due to the dual component used in the design, the maximum current value applies to two consecutive channels of the card, and this limitation must be taken into account. For example, for any two consecutive channels, the 100mA limit shared between the two channels can be distributed as follows:

• First and second channel driving 50mA each

• First channel at 80mA and second channel at 20mA

• First channel at 0mA and second channel at 100mA

• etc.

Installation

The OP7817 digital output signal conditioning module must be inserted at the back of the OP7000 simulator. The card can be installed in any of the 16 back slots, provided the front slot configuration is compatible. Refer to the page OP7000V2: Adding or Replacing Boards for more information on digital I/O card placement in the chassis - the same applies to the OP7000 chassis.

Make sure that the board is properly aligned using the guide tracks before pressing it into place.

Face Plate

The faceplate provides a DB37F connector. See “Connector Pins Assignment” below for details.

DB37F Connector Pins Assignment

Specifications