Circuit Model Section

Page Content

1 Circuit Model Configuration Page
2 Circuit Model Section Channels
3 eHS Solver
4 eHS Circuit Loading Behavior
5 Scenarios
6 Passive Elements
7 Related Links

Circuit Model Configuration Page

In the System Explorer window configuration tree, expand the Power Electronics Add-On custom device and select a Circuit Model section to display this page. Use this page to add an electrical model to the VeriStand System Definition. When the VeriStand project is deployed, the circuit model is simulated on the FPGA through the eHS Solver.

This page includes the following components, configurable at edit-time only:

Model
Name	Specifies the name of the circuit model.
Description	Specifies a description for the circuit model.
Circuit Model File Path	Specifies the path to the circuit model file on disk. When a file path is added or modified, the model file is parsed and VeriStand channels are created corresponding to the Source, Switch, and Measurement components defined in the circuit model. Component configuration settings are set to their default states.
Reload	Parses the currently specified circuit model and updates the VeriStand channels. Components whose names have not changed retain their previously configured settings, while new or modified components are reset to the default state. Components that are no longer part of the model are removed.
Clear	Removes the currently loaded circuit model. When a circuit model is cleared, the corresponding Source, Switch, and Measurement sections are deleted from the Configuration Tree and all related mapping configuration settings are removed.
Applied Timestep (s)	Specifies the execution timestep of the circuit model. The configured value must be between the Minimum Timestep (s) and the Maximum Timestep (s).
Optimize Solver Timesteps	Optimizes the execution timestep of the circuit model for best performance when the circuit model is coupled to machine solvers. By default, this checkbox is enabled. When Optimize Solver Timesteps is enabled, the Power Electronics Addon will calculate the optimal timestep for the circuit model in relation to other solvers in the VeriStand project, such as Machines. The Applied Timestep (s) control will be disabled for editing in this case. In most cases, it is recommended to enable this feature as it ensures that the circuit model and machine solvers are properly synchronized to each other for optimal simulation results.
Form Factor	Displays the Form Factor of the eHS Solver that will be used to simulate the circuit model. The form factor is dependent on the selected Hardware Configuration.
Circuit Model File Warning	If the file at Circuit Model File Path has been modified on disk since the circuit model was last loaded, the following warning message is displayed: Circuit model file has been modified on disk. Click Reload to ensure that the currently loaded model is up to date with the version on disk. Reloading the model clears the warning message.
Scenario Configuration
The components in this subsection are disabled until a circuit model has been loaded. Microsoft Excel is required to use the Scenarios feature.
Scenarios File Path	Specifies the path to the Scenarios file on disk.
New	Creates a new Scenario template file with the name and path specified in Scenarios File Path. The specified file must have the extension .xls.
Use Scenarios?	Enables the Scenarios feature in eHS. When enabled, the Scenario ID channel is added to the Configuration Tree.
Model Information
Minimum Timestep (s)	Displays the smallest timestep at which the eHS Solver can simulate the circuit model. eHS will run the simulation at this timestep by default, unless a larger timestep is specified in the Timestep (s) field.
Maximum Timestep (s)	Displays the largest timestep at which the eHS Solver can simulate the circuit model.
Number of Scenarios Used	Displays the number of Scenarios defined in the currently loaded Scenarios file.
Maximum Number of Scenarios	Displays the maximum number of scenarios that can be configured in the Scenarios file.
Refresh	Reanalyzes the circuit model file to refresh the information displayed under Model Information.

Circuit Model Section Channels

This section includes the following custom device channels. The value of an input channel can be modified dynamically at execution time.

Channel Name	Type	Default Value	Description

Channel Name

Type

Default Value

Description

Scenario ID

Input

0

Specifies the index of the scenario to be simulated. Modify the value of this channel at run-time to switch between scenarios.

This channel is only available when Use Scenarios? is enabled.

eHS Solver

The OPAL-RT electric Hardware Solver (eHS) is a floating-point solver that enables the simulation of an electric circuit on an FPGA without having to write the mathematical equations. It combines the simplicity of building electric circuit models using circuit editing software with the strength of FPGA-based simulators to solve for the circuit currents and voltages in real-time, with a sample time below 1µs.

The eHS Solver uses Modified Nodal Analysis to generate a conductance matrix that, when solved, returns the voltage at each node of the circuit and the current in each branch. The conductance matrix of the circuit is generated independently from the state of the switches, and therefore does not need to be recomputed when a switch is opened or closed during the simulation. This is achieved through the implementation of the Pejovic method, which represents each Switch component as an impedance–a conducting switch is represented as an inductor and an open switch is represented as a capacitor.

The components within the electric circuit model can be classified into four different types, listed below. See How to Create a Circuit Model for more information regarding the requirements of the circuit model file.

eHS Form Factors

The eHS solver is available in various form factors. Each form factor provides different capabilities for the number of Sources, Switches, Measurements, and Passive Elements that can be simulated.

Features	eHSx16	eHSx32	eHSx64	eHSx128

Features	eHSx16	eHSx32	eHSx64	eHSx128
Number of Sources	16	32	64	128
Number of Switches	12	48	72	144
Number of Measurements	16	32	64	128
Number of Resistors	Unlimited
LCA Capability*	Yes
Estimated Maximum Number of States**	84	112	168	344
Supported Switch Types	IGBT/Diode, Diode, Breaker, Thyristor, Ideal Switch. See Supported Circuit Editors for complete list.
Supported Non-Switching Devices	Resistor, Inductor, Capacitor, Ideal Transformer, Mutual inductance, PI Line. See Supported Circuit Editors for complete list.
Calculation Power (GFLOPS)	6.4	12.8	25.6	51.2
Maximum Number of Scenarios	Up to 512. Limit depends on circuit complexity.

* LCA, or Loss Compensation Algorithm, optimizes losses for standard topologies such as 2-level converter and NPC 3-level converter arms.
** The maximum number of states also depends on the number of inputs and outputs. There is no hard coded limit.

eHS Circuit Loading Behavior

Mapping and configurations settings applied to the Source, Switch, Waveform, and IO pages are preserved by saving the System Definition file. In certain cases, such as when loading a new circuit model file, these parameters may be reset to their default values.

The following actions cause the Source and Switch configuration settings to be reset to their default state:

Renaming the circuit model file on disk and loading the file.
Moving the circuit model file on disk and loading it from the new path.

In the following situations, all existing mappings and configuration settings are preserved (Sources, Switches, Waveforms, Analog Outputs, and Digital Outputs):

The circuit model file is unchanged and reloaded, either by browsing to the same Circuit Model File Path, or by clicking the Reload button.
Sources, Switches, or Measurements are added or removed, then the circuit model file is reloaded. Note that Source and Switch component mappings are only preserved for components whose names have not changed.
Changes are made to the passive elements, then the circuit model file is reloaded.

Scenarios

A Scenario is a version of the circuit model that has its own parameter settings for any passive element in the model. The Scenarios feature makes it possible to have multiple versions of the circuit model stored in the FPGA solver core. As the simulation is running, users can modify the value of the Scenario ID channel to switch from one Scenario to another and modify the model behavior. For example, this feature can be used to apply short or open circuit faults.

The Scenarios are managed from an XLS file. A row is defined for each Scenario, while the passive components are each assigned a column in the spreadsheet. For a given Scenario, it is possible to modify as many component values as required. At execution time, users can switch between Scenarios by manipulating the value of the Scenario ID channel. The maximum number of Scenarios allowed is dependent on the complexity of the circuit model, and is indicated by the Maximum Number of Scenarios parameter under Model Information.

For a step-by-step guide to setting up Scenarios and generating the XLS Scenarios file, refer to How To Use the Scenarios Feature.

Passive Elements

Passive elements are circuit model components such as resistors, inductors, and capacitors. Their properties cannot be changed or updated during the simulation unless Use Scenarios is enabled. See Supported Circuit Editors for a list of supported passive elements in the circuit model.