Power Electronics Add-On Custom Device

Ribbon Buttons

Add License

Launches the OPAL-RT License Manager dialog window. Browse to a deployment license file to install it to the host machine.

Right-Click Menu

Enable/Disable

Specifies if the Power Electronics Add-On real-time engine is Enabled or Disabled.

Power Electronics Add-On Main Page

Version

Specifies the version of the Power Electronics Add-On.

Configuration Description

This field is empty by default but can be updated by the user to provide context related to the configuration (hardware and circuit) setup

Target

Name of the FPGA target onto which the corresponding Circuit will be deployed.  This must match the name of the FPGA target as displayed in the NI Measurement and Automation Explorer.

Circuit

File name of the circuit model to be deployed to the FPGA target.

Target Credentials

Username

Specify the username for the NI Real Time Target.  The default target username is admin. Target credentials can be modified in the NI Measurement and Automation Explorer.

Password

Specify the password for the NI Real Time Target.  The default target password is an empty string. Target credentials can be modified in the NI Measurement and Automation Explorer.

Advanced Performance

Enable Telemetry Channels

Allows telemetry parameters to be exposed as VeriStand Channels. See Telemetry Channels below for more details.

Processor Assignments

Launches the Processor Assignments dialog window.

Advanced Channels

Telemetry Channels

Contains the Telemetry Channels. This section is made available when Enable Telemetry Channels is enabled.

FPGA Communication Process 1

Actual Loop Rate

The execution rate of the FPGA Communication Process.

Iteration

The iteration count of the FPGA Communication Process.

Write Time

Time taken by the FPGA Communication Process to write the values of the input VeriStand channels to the FPGA model inputs.

Read Time

Time taken by the FPGA Communication Process to read the outputs of the FPGA models and publish them to the output VeriStand Channels.

Iteration Duration

Time taken to execute the last entire iteration of the process.

Finished Late Count

Number of iterations that have exceeded the specified Loop Rate for this process.

FPGA Communication Process 2

Actual Loop Rate

The execution rate of the FPGA Communication Process.

Iteration

The iteration count of the FPGA Communication Process.

Read Time

Time taken by the FPGA Communication Process to read the outputs of the FPGA models and publish them to the output VeriStand Channels.

Write Time

Time taken by the FPGA Communication Process to write the values of the input VeriStand channels to the FPGA model inputs.

Iteration Duration

Time taken to execute the last entire iteration of the process.

Finished Late Count

Number of iterations that have exceeded the specified Loop Rate for this process.

Low Latency FPGA Communication Process (One per FPGA Target with Low Latency Support)

Actual Loop Rate

The execution rate of the Low Latency FPGA Communication Process.

Iteration

The iteration count of the Low Latency FPGA Communication Process.

Write Time

Time taken by the Low Latency FPGA Communication Process to write the values of the input VeriStand channels to the FPGA model inputs.

Read Time

Time taken by the Low Latency FPGA Communication Process to read the outputs of the FPGA models and publish them to the output VeriStand Channels.

Iteration Duration

Time taken to execute the last entire iteration of the process.

Finished Late Count

This data is not available for Low Latency FPGA Processes.  The channel value is always -1.

Late Samples

Number of samples that have been sent late from the Low Latency Process to the Low Latency Engine on the FPGA. This indicates that the CPU has fallen behind.

FPGA System Loop Time

Measured execution rate of the Low Latency Engine on the FPGA.

CPU Load Time Value

Time measured from the start of the FPGA-to-CPU write data transfer to the completion of the CPU-to-FPGA read data transfer.

CPU Load Time Maximum

Maximum CPU Load Time Value.

Transfer Sequence Number

FPGA-to-CPU Transfer Sequence Number. This value is incremented by the FPGA engine after the FPGA-to-CPU data is transferred to the CPU.

FPGA Communication State

Last reported state of the Low Latency Engine on the FPGA.

Waveform Acquisition Process

Actual Loop Rate

The execution rate of the Waveform Acquisition Process.

Iteration

The iteration count of the Waveform Acquisition Process.