Block

Mask

Description

The Op5130 Ctrl block accesses the Opal-RT Active FPGA carrier board (OP5130).

The OpCtrl blocks and the OpFcn blocks are designed in order to separate board access and data treatment to and from the boards. This OpCtrlblock attempts to detect an OP5130 Active FPGA Carrier board connected to an OP5110 card via a SignalWire link. Once the hardware is detected, the OpCtrl block relays the data to and from the OP5130 board to the OpFcn functionality blocks. The OpFcn functionality blocks perform data treatment such as scaling.

OpFcn blocks are linked to an OpCtrl block through the controller name specified in both the OpFcn and OpCtrl blocks. Since the number and type of available functionalities on each board are different, each OpCtrl block driver registers a set of available functionalities that represent the different components of the board it represents.The Op5130 Ctrl block supports the OpFcnAnalogOutput, OpFcnAnalogInput and OpFcnStatusRegister functionalities.Please refer to the documentation of the OpFcnAnalogInput, OpFcnAnalogOutput and OpFcnStatusRegister blocks for more details on these functionalities.

Note: Please refer to the Characteristics and limitations section below for information regarding model synchronization with an OP5130 board.

Parameters

Controller Name	The controller name uniquely specified in an OpCtrl block's parameter enables the binding between a specific controller and the functionality blocks it supports. Search Strategy: the OP5130 board is a SignalWire based hardware, i.eit is a remote board that communicates via the Opal-RT SignalWireprotocol with a local PCI board (typically an OP5110 board). The default strategy for binding an Op5130 Ctrl block with an OP5130 board is 'First Available', and it will attempt to detect OP5130 boards and will bind the controller to the first OP5130 detected on the SignalWirecommunication link. It is convenient for most applications requiring only one OP5130 board. For other Search Strategies, additional identification parameters appear depending on the Search Strategy selected.
ChassisID	This parameter appears only if the Search Strategy 'Specific location in a chassis' was selected. Please refer to TestDrive chassis documentation for information on how to select or read the chassisID of a TestDrive chassis.
SlotID	This parameter appears only if the Search Strategy 'Specific location in a chassis' was selected. The Slot ID is the slot number in which the board is inserted, slot #1 being the left-most slot when looking at the front of the chassis.
Board ID	This parameter appears only if the Search Strategy 'Specific location on a communication link ' was selected. It refers to the Board Index of the OP5110 board connected by SignalWire to the remote OP5130 board. It is determined by the selection of theJP8 jumpers of the OP5110 board. Please refer to the OP5110 documentation for more information.
Port Number	This parameter appears only if the Search Strategy 'Specific location on a communication link ' was selected. It refers to the SignalWire port of the OP5110 board where the SignalWire cable linking the OP5130 to the OP5110 is connected. Typically, you should enter 0 if you are using an OP5110 board with a bitstream that supports only one SignalWire port. For multi-SignalWire-port OP5110 boards, please refer to the OP5110 bitstream definition.
Node ID	This parameter appears only if the Search Strategy 'Specific location on a communication link ' was selected. Node identification depends on the SignalWire backplane on which the OP5130 board is installed. Please refer to the documentation of your system for information on node identification.
Sample Time (s)	This parameter allows the user to specify the sample time for this block, and its associated TestDrive board, in seconds. The default value is 0, which specifies a continuous sample time (note that the sample time is borrowed from the separated subsystem). Some rules must be respected: All TestDrive controller blocks sharing the same SignalWire port must have the same sample time. A controller block and its related functionality blocks must share the same sample time. If an OpConfigSync block is used and does not specify the SignalWire port of the module as the synchronization source, the sample time must be an integer multiple of the synchronization source sample time specified in it. If an OpConfigSync block is used and specifies the SignalWire port of the module as the synchronization source, its sample time must be the fastest rate in the model. Multi-tasking is not supported. To execute the TestDrive boards at a rate slower than the rest of the model, use a multi-core TestDrive system. Group the TestDrive blocks in a slower slave subsystem. Then, create another subsystem, containing the OP5110 synchronization block and execute it in XHP mode at the fastest rate. Also, an OpConfigSync block must be used to specify the synchronization source. If multiple SignalWire ports are used, the board must execute at the model base rate. Multi-rate is not supported with multi-port SignalWire.

Inputs

This block has no inputs.

Outputs

This block has no outputs.

Characteristics and Limitations

Synchronization

The OP5130board can be used in Hardware synchronized mode, both in master and slave mode. In both modes, the OP5130 is programmed with the calculation step of the model and its inputs and outputs are updated at each calculation step. In master mode, the OP5130 is the board that synchronizes the model, i.e. the synchronization signal of the OP5130 determines the beginning of each calculation step. In slave mode, the OP5130 accepts a synchronization signal from another IO board such as the OP5110board and it synchronizes the update of the inputs and outputs with this external signal. For cabling issues regarding the external synchronization signal, please refer to the documentation coming with your system or contact support@opal-rt.com.

In an application using only one SignalWire port, if no OP5110-5120 Opsync is used, the synchronization of the model is controlled by the module with the highest slot number on a given SignalWire port. This mechanism ensures that status messages coming from all modules are received before the end of the calculation step signal is sent to the model.

However, if an OP5110-5120 Opsync block or multiple SignalWire ports are also used, an OpConfigSync block must be inserted in the model in order to specify which component will control the synchronization. Please refer to the documentation of the OpConfigSync for more details.

Note: In Software Synchronized mode, the time base of the OP5130is not synchronized with the rest of the model, which may cause glitches on waveforms of Analog Output modules. It is therefore not recommended to use these modes.

Connector Pin Assignments

The table below gives the connector pin assignment of the 96pin external connector of the OP5130 board. The OP5130 can hold two mezzanine modules. The modules are usually referred to as module A and module B (as indicated on the OP5130 board). The table below is thus divided into two sections, one for the pin assignment of module A, and one for module B. In each section, the connector pin assignment is indicated for each type of supported mezzanine module.

Direct Feedthrough	No
Discrete sample time	Yes
XHP support	Yes
Work offline	No

RT-LAB Documentation

Op5130Ctrl