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The RCP PWM Out block is a PWM (Pulse Width Modulation) signal generation module. The goal of this generation block is to maintain constant synchronicity between the PWM signals and the user model period being executed on the CPU. The time steps selected for your model will, therefore, determine the frequencies that the PWM can reach.


Controller NameBind this block to an OpCtrl block by entering the same 'Controller Name' as specified in the OpCtrl block The OpCtrl block controls initialization of the settings of one specific Opal-RT card (OP5142/ML605/OP7160) in the system.
DataIn port numberEnter the index of the DataIn port to be controlled by this block, in the range [1:32].
Slot infosThis non-editable parameter displays the physical location of the digital output channels related to the selected DataIn port, as obtained from the parsing of the configuration file.
Maximum number of PWM signals controlled by this blockThis non-editable parameter displays the number of channels in one sub-section listed in the configuration file.
Number of PWM signalsEnter the number of independent PWM signals
PeriodThis parameter retrieves the model's step size.
Delay between step beginning and PWM period beginningThis parameter is the time, in seconds, between the start of the CPU model's time step and the start of the PWM period.
Trigger Pulse sourceThis parameter selects the PWM signal that triggers analog acquisition.
Trigger Pulse TypeThis parameter selects when analog inputs will be acquired for the previously selected channel, either beginning or mid-period or both.
PWM Period/Model period Ratio [1-255]This parameter sets the ratio between the CPU model timestep duration and the PWM period duration. Allows the definition of the PWM frequency, which must be an integer between 1 and 255. 
Frequency estimation[Hz] This parameter estimates PWM frequency according to the current model timestep.
PWM Carrier TypeThis parameter selects a waveform of carrier. (Symmetrical or Asymmetrical Modulation).
Update time of duty cycleThis parameter selects the instant of duty cycle update. The update could be done, either the beginning or middle of the period or both.
Phase [deg]This parameter set PWM period dephasing, by degrees. The value sent to the FPGA is this value modulo 360 degrees
Pinout Assignment TabThis parameter is used to route PWM signals to the proper output channels.
Deadtime [0 - 20e-6 sec]This parameter sets the dead time between the fall time from high to low PWM state and the rise time of the complementary.


Duty cycleThis input is the duty cycle. It should be inside the [0,1] range. When the value is out of range, the duty cycle is saturated.
StopThis input is used to stop the PWM generation. A rising edge on this input stops the PWM generation. Only a rising edge on Restart Input can restart the PWM generation.
RestartThis input is used to restart the PWM generation. A rising edge on this input restarts the PWM generation. This input's action is effective after a rising edge on Stop input.


This block has two outputs.

SyncData: This output returns the synchronization vector that will be used by the RCP Analog In block to start its acquisition. The first data is the period of acquisition, the second is the instant of first acquisition. If 'Trigger Pulse Type' parameter is set to 'Both', a third data is outputted to specify the second acquisition instant.

Status: This output returns the following values:

0No error.

Block could not be matched with an OpCtrl (check the 'controller Name' value), or FPGA card initialization problem.

-2Internal memory initialization problem.

Characteristics and Limitations

Direct FeedthroughNo
Discrete sample timeInherited
XHP supportYes
Work offlineNo

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