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OpCtrl Reconfigurable IO
Block
Mask
Description
This controller block accesses a user-selectable Reconfigurable IOcard. Reconfigurable IO cards are cards that can be reprogrammed at will with different bitstreams, allowing the user to run different applications with the same hardware.
The OpCtrl ReconfigurableIO block provides a standard interface for writing data to and receiving data from, the reconfigurable card. Since the OpCtrl ReconfigurableIO block has no knowledge of the specific bitstream programmed into the flash memory of the card, it is the responsibility of the user to ensure that data are written to the inports (or read from the outports) of the block in the order required by the bitstream programmed into the board.
The block supports Opal-RT OP5130 board. Support for other Opal-RT boards is in progress.
The OpCtrl ReconfigurableIO block does not manage the programming of the flash memory of the board. This programming must have been performed before running RT-LAB, with the appropriate application. See the Characteristics and Limitations section below for indications on card programming and for information regarding model synchronization.
Parameters
| Controller Name | Typically, the controller name uniquely specified in an OpCtrl block's parameter enables the binding between a specific controller and generic functionality blocks. |
|---|---|
| Board Type | Select the board type in this list. OP5130-SYSGENrefers to Opal-RT OP5130 card programmed with a bitstream produced with RT-XSG. See the Characteristics and Limitations section below for more details. Note that OP5110-SYSGEN is not supported. |
| Search Strategy | This popup appears only if OP5130-SYSGENis selected for the Board Type. OP5130 is a SignalWire based hardware,i.e it is a remote board that communicates via the Opal-RT SignalWireprotocol with a local PCI board (typically an OP5110 board). The default strategy for binding an OpCtrl Reconfigurable IO block with an OP5130 board, 'First Available', will attempt to detect OP5130boards and will bind the controller to the first OP5130 detected. It is convenient for most applications requiring only one OP5130 board. For other Search Strategies, additional identification parameters appear depending on the Search Strategy selected. |
| Chassis ID | This parameter appears only if the Search Strategy'Specific location in a chassis' was selected. Please refer to TestDrivechassis documentation for information on how to select or read the chassis ID of a TestDrive chassis. For the HIL system, the default ID is 1.The command /usr/opalrt/common/bin/flash_update -bim provides the chassis ID. |
| Slot ID | This parameter appears only if the Search Strategy'Specific location in a chassis' was selected. The Slot ID is the slot number in which the board is inserted, slot #1 being the left-most slot when looking at the front of the chassis. |
| Board ID | This parameter appears only if the Search Strategy'Specific location on a communication link ' was selected. It refers to the Board Index of the OP5110 board connected by SignalWire to the remote OP5130 board. It is determined by the selection of theJP8 jumpers of the OP5110 board. Please refer to the OP5110 documentation for more information. |
| Port Number | This parameter appears only if the Search Strategy'Specific location on a communication link ' was selected. It refers to the SignalWire port of the OP5110 board where the SignalWire cable linking the OP5130 to the OP5110 is connected. Typically, you should enter 0 if you are using an OP5110 board with a bitstream that supports only one SignalWire port. For multi-SignalWire-port OP5110 boards, please refer to the OP5110 bitstream definition. |
| Node ID | This parameter appears only if the Search Strategy'Specific location on a communication link ' was selected. Node identification depends on the SignalWire backplane on which the OP5130 board is installed. Please refer to the documentation of your system for information on node identification. |
| PCI Index | This parameter appears only if the Board Type selected is a PCI board. See the glossary definition. |
| Number of Inports | Enter the desired number of inports for this block. It should be an integer between 0 and 16. |
| Number of Outports | Enter the desired number of outports for this block. It should be an integer between 0 and 16. |
| Xsg Model Name | This is the name of the FPGA XSGmodel associated with the OpCtrlReconfigIO block. This will be the FPGA model used for bitstream compilation and for offline simulations. These two actions can only take place if an XsgManager block is found in the same model as the OpCtrl ReconfigurableIO block. Simulation and bitstream compilation will be performed according to the settings found in the XsgManager. The "Xsg ModelName" field can be left empty if you do not need to refer to an XSG FPGA model, for example, if the 'Bitstream File Name'parameter specifies a bitstream that was previously generated and is already available in the model directory. |
| Bitstream FileName | This is the name of the bit stream expected to be programmed on the OP5130 before the model is loaded. The programmatic of the OP5130 is performed by RT-LAB during the load stage. The bitstream must be available in the model directory. Note that if an XSG Manager block is present in the model, and if the 'Rebuild options' of the Xsg Manager block is set to anything other than 'Never', the value entered for the 'Bitstream File Name' will be ignored and the name of the bitstream that will be programmed is determined by the Board Type parameter and the parameters entered in the Version block located in the FPGA model. |
| Use External Send/Recv blocks | This option is available only with the OP5130-SYSGEN board type. When this option is checked, the inports and outports of this block are removed and data is transmitted to and from the OP5130 board via the OpFcnXSGRecv and OpFcnXSGSend functionality bocks. This option allows for more flexibility in the Simulink model design. Note that this option should not be checked if the XSG FPGA model is to be played offline. |
| Show Advanced Diagnostics output | This option is available only with the OP5130-SYSGEN board type. When this option is checked, a status output is added to the block. See the Outputs section for details on the status values. |
| Return External Carriers ID codes | When this option is checked, an additional output is added to the block in order to return the IDcodes of the hardware connected to the OP5130 via its backplane connector. See the Outputs section for more details. |
| Return Mezzanine ID codes | When this option is checked, an additional output is added to the block in order to return the ID codes of the mezzanine modules installed in slot A and B of OP5130. See the Outputs section for more details. |
| Sample Time (s) | This parameter allows the user to specify the sample time for this block, and its associated TestDrive board, in seconds. The default value is 0, which specifies a continuous sample time (note that the sample time is borrowed from the separated subsystem). Some rules must be respected:
|
| Set ports data type to double | Set the data type of inports and outports to 'double' instead of 'unsigned int'. The data in and out of the block are still raw 32bit values. |
Inputs
The number of inports is controlled by the mask parameter 'Numberof Inports'. The type of the inports is unsigned 32-bit. When used with an OP5130 board, the size of each inport can be up to 253 values.
At each calculation step, these input values are written to the data input registers of the board.
Outputs
The number of outports is controlled by the mask parameter Number of Outports. Each outport is a vector of unsigned 32-bitvalues. The width of each output is defined by the surrounding model but must remain consistent with the capabilities of the bitstream programmed into the reconfigurable board.
At each calculation step, the data output registers of the board are copied to the outputs of the block.
Three additional outports are available if the Board Type selected is OP5130-SYSGEN. These outports return double values.
- The Error outport returns the following error codes:
| Value | Description |
|---|---|
| 0 | No error. |
| -1 | Card not detected |
| -2 | Mismatch between the amount of output data received from the board and the width of the output ports or SignalWire communication problem |
| -3 | This error indicates that the synchronization unit of the OP5130 cannot ensure proper synchronization with the RTSI pulse it receives. This can indicate a problem with the 100MHz oscillator of the OP5130. It can also happen when the time step of the model is beyond the supported range (0 - 41.9ms) |
| -4 | Synchronization timeout error. This error occurs when the OP5130 is programmed in slave mode and no RTSI pulse is provided, for example if the RTSI cable is unplugged. |
| -10 | This error code can be added to the above codes. It indicates a mismatch between the type of hardware selected in BP_A_IO and BP_B_IO blocks in the FPGA model and the actual hardware connected to the OP5130 backplane connector. |
| -100 | This error code can be added to the above codes. It indicates that at least one of the mezzanine slots of the OP5130 is left empty. |
- If the Parameter 'Show Advanced Diagnostics output' is checked,a Status outport is added to the block. This outport is used to debug communication problems with the OP5130-SYSGEN board and especially to detect mismatches between the data received from the board and the data expected to be received.. The width of this outport is equal to the number of data outports specified by the 'Number of Outports'parameter. The elements of the vector contain the number of data values received from the board for each output port.
- If the Parameter 'Return External Carriers ID codes' is checked, the IDs outport is added to the block. This outport is used to return identification information regarding the hardware connected to the OP5130 board via its backplane connector. Each type of hardware that can be connectedto the backplane connector of the OP5130 and selected in the BP_A_IOand BP_B_IO of the FPGA model holds a different ID code. Values are in the range 0 to 63 ('0' to '3F' in hexadecimal). The actual hexadecimal value assigned to each hardware can be found by looking at the BoardID block under the mask of the BP_A_IO and BP_B_IO blocks of the FPGA model. Note that the OP5120 carrier does not have an ID code and returns the value 63. This is also the value returned when the adaptor card connected at the back of the OP5130 is not and OP5929 or when the BoardID cable of the OP5929 adaptors (JP9) is not plugged. Bitstreamsproduced with older RT-LAB versions do not support the ID codes feature, and the IDs outport returns -1 when such a bitstream is programmed in the OP5130.
- If the Parameter 'Return Mezzanine ID codes' is checked, the MezzIDs outport is added to the block. This outport is used to return identification information regarding the mezzanine modules installed in slot A and B of the OP5130. Values are in the range 0 to 63 ('0' to '3F' in hexadecimal). The OP5130 supports two types of mezzanine modules: OP5330 (D/A) and OP5340 (A/D). The OP5340 has MezzID=1, the OP5330 family consists in OP5330-1 (MezzID=0), OP5330-2 (MezzID=2) and OP5330-3 (MezzID=3). If a slot of the OP5130 was left empty, the MezzId value returned for this location is 63 ('3F'). Bitstreams produced with older RT-LAB versions do not support the ID codes feature, and the MezzIDs outport returns -1 when such a bitstream is programmed in the OP5130. Note that the Error output reports an error only if a slot is left empty.
Characteristics and Limitations
Board Programming
Opal-RT boards: The OpCtrl Reconfigurable IO block only supports the OP5130 board for now and the OP5110 boards in future releases. The bitstreams for these boards are generated from Windows in Matlab/Simulink using the XSG Manager and the Xilinx system generator toolbox, and the bitstream template provided by Opal-RT. Once the bitstream generated it must be programmed into the Flash memory of the board on QNX6, with the flash_update application that comes with RT-LAB.
Note that OP5130 reconfigurable bitstreams (to be used with the OpCtrlReconfigurable IO block) can be differentiated from OP5130 standard bitstreams (to be used with the Op5130 Ctrl block) by the ProductMinor ID. The Product Minor Id is 1 or higher for a reconfigurableOP5130 bitstream, and 0 for a standard OP5130 bitstream. This Id is returned in the Board Identification Message obtained when flash_update-bim is run on the target. It is also the 5th token of the bitstream name (ex: S17-0024-AC-18-1-xxx.bin or higher refers to a reconfigurable bitstream, and S17-0024-AC-18-0-33.bin refers to the standardOP5130 bitstream).
Synchronization
The OP5130board can be used in Hardware synchronized mode, both in master and slave mode. In both modes, the OP5130 is programmed with the calculation step of the model and its inputs and outputs are updated at each calculation step. In master mode, the OP5130 is the board that synchronizes the model, i.e. the synchronization signal of the OP5130 determines the beginning of each calculation step. In slave mode, the OP5130 accepts a synchronization signal from another IO board such as the OP5110board and it synchronizes the update of the inputs and outputs with this external signal. For cabling issues regarding the external synchronization signal, please refer to the documentation coming with your system or contact support@opal-rt.com.
In an application using only one SignalWire port, if no OP5110-5120 Opsync is used, the synchronization of the model is controlled by the module with the highest slot number on a given SignalWire port. This mechanism ensures that status messages coming from all modules are received before the end of the calculation step signal is sent to the model.
However, if an OP5110-5120 Opsync block or multiple SignalWire ports are also used, an OpConfigSync block must be inserted in the model in order to specify which component will control the synchronization. Please refer to the documentation of the OpConfigSync for more details.
Note: In Software Synchronized mode, the time base of the OP5130 is not synchronized with the rest of the model, which may cause glitches on waveforms of Analog Output modules. It is therefore not recommended to use these modes.
| Direct Feedthrough | No |
|---|---|
| Discrete sample time | No |
| XHP support | Yes |
| Work offline | No |
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