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  • This document describes the Spectracom TSync PCIe Controller block. This board is a synchronized timecode reader/generator offering flexibility and easy integration of precise timing into an embedded computing application.
  • The controller block configures the board to generate an external signal synchronized with the model's calculation step size. The pulse width is 40 nanoseconds. If the decimation factor changed during the pause state, the pulse frequency is updated when the model execution resumes.
  • When the 'Generate timestamp' option is enabled, the block also sends the following timestamp information into an 8-wide output bus: year, day of the year, hour, minute, second, nanosecond, epoch time and a synchronization flag. The timestamp is in the format provided by the synchronization source and is only valid when the synchronization flag is set. It is recommended to set your synchronization source to always provide a timestamp in UTC format and if required, to perform at the appropriate conversion in the model to match your local time.
  • Timestamp output should be disabled if it is not used in your model. This will increase the CPU time available for computation. The timestamp output is only being updated when the timestamp enable input is active.
  • If the 'Generate timestamp' option is enabled, the 'Synchronize system time' option can be used to set the system time with the generated timestamp information. The system time will be set considering the timestamp is in UTC format and only if the TSyncPCIe card is synchronized.
  • If the 'Generate timestamp' option is enabled, the user must specify what will be sent to the timestamp output in the case the TSync PCIeboard is not synchronized.
  • The synchronization flag is 1 as soon as the board receives a valid reference input. When the reference is lost, the holdover timer is decreased until it reaches zero, then the synchronization flag is set to 0. Therefore, a synchronization flag of 1 means that the reference input signal is valid, or that the board is in holdover state.
  • To operate, the block loads the TSYNCPCI driver integrated into the Opal PCI library.


General Parameters

Device IDThis parameter identifies which TSync PCIe board to control in the case where multiple boards are present on the system.
Holdover timeoutThe holdover timeout argument is the number of seconds that can be tolerated without having a valid input signal to be used as a reference, before asserting the synchronization flag to 0. During the holdover state, the time is maintained by an internal oscillator.
Generate timestampEnable or disable the timestamp output. It should be disabled if not used by the model.
Synchronize system timeEnable or disable the system time synchronization. It should be disabled if the system time is synchronized with another source, or if changing the system time can have undesirable impacts on the system behaviour.
Without synchronization, timestamp with

Select what will be sent to the time stamp output if the TSync PCIe board is not synchronized:

  • UTC 0: set all the signals of the timestamp bus to 0.
  • Simulation time: set the timestamp output to the time elapsed since the start of the simulation. If the system was synchronized and the synchronization is suddenly lost, the timestamp will continue to increment from the previous value using the internal board oscillator. The timestamp cannot be considered as accurate when this situation happens.
  • System time: set the timestamp the current system time.


When 'Generate timestamp' option is enabled:

TS enabled: This input can be used to control the timestamp output refresh rate.


When 'Generate timestamp' option is enabled:

TS: This output bus provides the following timestamp information:

1Day of year
6Epoch time

The timestamp output can be easily demuxed as shown in the following example:

Characteristics and Limitations

The Spectracom TSync PCIe board supports multiple prioritized timing inputs. When an input is lost, the unit automatically switches to the next input in order of priority.

The disciplined onboard oscillator is phase-locked to an external timing input, providing 5ns resolution time. This 10 MHz oscillator, central to the TSync-PCIe timing functions, uses the last known reference to increment("freewheel") in the absence of a timing input.

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