Specifications
IO Capabilities
This configuration requires the following FPGA boards. Please refer to the linked product page for additional information.
The PXIe-7868R supports the following features:
IO Type | Details |
|---|---|
Analog Input | 6 CH, 1MS/s, 16-bit, +/- 10V Input Signal Range, Differential Tunable Gain, Offset, and Min/Max Saturation |
Analog Output | 18 CH, 1MS/s, 16-bit User-defined mapping to Analog Outputs available with tunable Gain, Offset, and Min/Max Saturation.
|
Digital Input | 16 CH, 80MHz, 3.3V TTL (Connector 1) |
Digital Output | 32 CH Total:
User-defined mapping to Digital Outputs available with tunable Polarity.
|
Refer to 7868 IO Pinout [eHSx32_Dual_PMSM_VDQ_IO_32DO_7868R]to see the IO assignment.
Modeling Capabilities
This configuration includes a pre-compiled firmware/bitfile which contains the following features:
Features | Low Latency Support |
|---|---|
⚫ | |
⚫ | |
1x Encoder/machine | ⚫ |
1x Resolver/machine | ⚫ |
⚪ | |
16x PWM Generators | ⚫ |
⚪ | |
18x Analog Outputs | ⚪ |
⚪ | |
32x Digital Outputs | ⚪ |
16x Digital Inputs | ⚪ |
⚪ | |
⚪ |
⚫ = Supported ⚪ = Not Supported
In features with Low Latency Support, data is transferred between the FPGA and Real Time VeriStand Channels through the Low Latency FPGA Communication Processes. For more information related to communication processes in the Power Electronics Add-On, refer to Processor Assignments.