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Table of Contents
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The I/O interface must be configured, and valid connections must be defined (using the Configuration section of the RT-LAB project) before the driver is launched at simulation start.

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Bitstream Configuration

Every bitstream file (.bin), or Versal boot Programmable Device Image (.pdi), programmed into an FPGA interfaced with the OPAL-RT Board driver must have an associated configuration file. The driver requires a description of the hardware installed in the simulator to correctly interface with it.

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  • Make sure the .opal file given by the field Bitstream configuration file exists.
    • If it doesn't exist, find it and copy it in the project directory.
  • Copy the .bin file to the project directory.
  • Close the project.
  • Re-open the project.

Users can also program the bitstream using RT-LAB's flash utility (see Flash bitstream wizard in RT-LAB Help files).

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For a list of the possible chassis and board/module combinations, consult the list of compatibilities in the Limitations section.

See the General Configuration section below for more details on changing and loading configurations.

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For a list of the possible remote chassis and board/module combinations, consult the list of compatibilities in the Limitations section.

Interface Overview

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The following options can be configured through the General section:

Chassis typeSelect the chassis used in the simulation.
    IP address

In order to allow bitstream programming, this field will be available for the user to enter the appropriate IP address that is displayed on the Chassis LCD.

NOTE: Only visible when Chassis type is OP4810 or OP4815.

    Chassis name

This field will be available for the user to configure a custom name to be displayed on the Chassis LCD.

NOTE: Only visible when Chassis type is OP4810 or OP4815.

Chassis IDEnter the chassis ID of the selected FPGA board in the simulation.


Use external synchronization source

When selected, the board uses an external synchronization source as opposed to its internal clock.
Operate as hardware synchronization source must be checked if the external synchronization source comes from another simulation (i.e. another model).

Type of generated synchronization signal

If the Use external synchronization source box above is unchecked, then this parameter is visible, allowing the user to choose the medium where the FPGA outputs its synchronization pulse: choices are through the optical cable or through the audio cable.

NOTE: Spartan-3 cards (OP5142) have only one type of synchronization signal, RTSI. This signal is routed to the necessary synchronization converters (audio or optical), according to the system's assembly.

Operate as a hardware synchronization source

Only visible if the Use external synchronization source checkbox above is enabled. 


  • When enabled, the FPGA is configured to use the external synchronization source received to synchronize the simulation (master-with-external-clock mode)
  • When disabled, the FPGA is configured to use the external synchronization source received but it will not qualify to drive the simulation (slave mode)
Type of expected synchronization signal

This parameter is only visible if the Use external synchronization source checkbox above is enabled. It is a drop-down menu giving the user the choice to synchronize either through copper or optical cables.

NOTE: Spartan-3 cards (OP5142) have only one type of synchronization signal, RTSI. This signal is routed to the necessary synchronization converters (audio or optical), according to the system's assembly.

Bitstream configuration locationThis field allows either searching the bitstream configuration file using the file system or selecting it from a drop-down list based on the available files in the standard OPAL-RT repositories.
Bitstream configuration file

If the bitstream configuration location is set to File system

  • A file-browsing field appears.
  • Clicking it opens a File Explorer window to navigate to the bitstream configuration file.

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This file must be in the [board_type]_[file_name].extension format.

The .extension can either be .opal or .opbin. Example: VC707_Config1.opal or VC707_Config1.opbin.



If the bitstream configuration location is set to Standard repositories:
A drop-down with the available configuration files found in the standard Opal-RT repositories appears.

Once a file is selected and the interface has checked validity, the Folders section of the configuration panel updates to show the I/O capability of each slot as described in the file.


Show advanced configuration

When selected, the user can configure advanced features:
Time step factorDenotes a multiplier for the board's speed in relation to the model's timestep.
Enable FPGA register logger

For advanced debugging purposes, the driver will start a tool that will log all the FPGA register accesses during the initialization and the reset of the model. The logs will be saved in files named with the prefix "register_trace*". Those files are retrieved on the host PC after the reset of the model.

Automatic bitstream reprogramming

If selected, bitstream programming is triggered automatically at the model load.

The bitstreams should be placed at the model path and must have the name given in the configuration file used.

If the bitstream currently programmed in the board is found to be the same as the one about to be programmed, then the bitstream is reloaded into the FPGA. The field is not available if the bitstream file is not Found.

Bitstream file nameA static field showing the bitstream found based on the selected bitstream configuration file.
ForceThis option flashes the board even if it is already programmed with the same bitstream.
Disable strict hardware mismatch validationIf selected, the use of multiple I/O card types based on general compatibility rules is activated instead of exact hardware ID values.
Enable FPGA ScopeIf selected, the FPGA Scope will be available when the model is executed. The option is visible only if the feature is available in the selected bitstream configuration file.
Enable virtual modeIn virtual mode, the model can be executed even if this I/O interface is not compatible with the hardware configuration of the system. The connections between the model and the I/O interface will be done during the initialization, but the I/O interface will not do anything. The virtual mode can be used to troubleshoot problems on a system without having the required hardware, or to prepare a model with different I/O interfaces even if the final hardware platform is not available.


For more information, contact OPAL-RT's Support team.

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When clicking this section, the fields provide the following information to the user:

DescriptionElectrical characteristics of the slot.
FunctionalityType and direction of the I/Os in the slot.
I/O card typeI/O board identifier.

Other parameters may appear here, depending on the I/O board type.

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1. Select a bitstream configuration file (the same or different) from the drop-down containing available configuration files when Bitstream configuration location equals to Standard repositories or by clicking on the Bitstream configuration file value when Bitstream configuration location equals to File system. This will bring up the refresh menu, asking how to proceed with the configuration's editable parameters that originated from the initial file. The parameters affected by this choice are the ones marked as keep or reset in the table below, in the Common elements update section.

Keep all modified valuesThe values of the editable parameters that originated from the initial bitstream configuration file will be unaltered. This will ensure that any user modifications are maintained.
Reset all modified valuesThe values of the editable parameters that originated from the initial bitstream configuration file will be reset to the value found in the new file. All user modifications will be lost

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4. The configuration can be reset when Bitstream configuration location equals Standard repositories. To do so, choose the option < Select your file > from the drop-down menu containing the available configurations.

Detecting changes in the bitstream configuration file

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Only Slot1B slot is considered in common :

  • Slot1A : the slot name is the same however the digital in cards in the new and old bitstream configuration files are not compatible (refer to section General Compatibility Rules for Multiple I/O Card Types). When the new bitstream configuration file is applied, the information and configuration of Slot1A will be reset to the values contained in the new .opal.
  • Slot1B: the slot name is the same and the analog out cards in the new and old bitstream configuration files are compatible (refer to section General Compatibility Rules for Multiple I/O Card Types). When the new bitstream configuration file is applied, the Slot1B IO card type is reset to the card type in the new file (OP5330-3), however the user configurations applied on the associated common channel groups will be kept.
  • Slot2A: only available in the old bitstream and will be removed when the new bitstream configuration file is applied.
  • Slot2B: only available in the new bitstream configuration file and will be added to the configuration when the file is applied.

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  • Port 0: kept, but only the first 2 previously configured DWORDS remain, as the new maximum DWORD count has changed to 2.
  • Port 1: removed due to not being defined in the new configuration file.
  • Port 2: added according to the new file.

Example 3: 

Both old and new bitstream configuration files specify support of the MuSE feature; the remote boards configured by the user will be kept when loading the new file.

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Common elementsActionExplanation










Slot configuration


DescriptionresetThe value of the Description field will be reset to the value in the new bitstream configuration file.
FunctionalityresetThe Functionality field will be reset to the value in the new bitstream configuration file.
IO card typeresetThe IO card type field will be reset to the value in the new bitstream configuration file.
Analog Inputs
keepThe Analog Inputs channel group configuration (refer to Analog In) is applied to the new configuration.
Analog OutputskeepThe Analog Outputs channel group configuration (refer to Analog Out) is applied to the new configuration.
Digital InputskeepThe Digital Inputs channel group configuration (refer to Digital In) is applied to the new configuration.
Digital OutputkeepThe Digital Outputs channel group configuration (refer to Digital Out) is applied to the new configuration.

Digital In channel group Threshold low value

keep or resetIf a slot contains a card with support for configurable thresholds (refer to section General Compatibility Rules for Multiple I/O Card Types), the Threshold low value from the old configuration is kept or reset according to the user preferences.

Digital In channel group Threshold high value

keep or resetIf a slot contains a card with support for configurable thresholds (refer to section General Compatibility Rules for Multiple I/O Card Types), the Threshold high value from the old configuration is kept or reset according to the user preferences.

Bidirectional channel group Direction

keep or resetIf a slot contains a card supporting configurable direction (refer to section General Compatibility Rules for Multiple I/O Card Types), the Direction is kept or reset according to the user preferences.




Raw data configuration

Raw data from board ports

keep

If both the old and the new bitstream configuration files define the same raw data from board ports, the configuration done (refer to section Data from Board on these ports is kept.

For all common ports, the maximum DWORD count is the lower value among the maximums defined in the two files.

Raw data to board portskeep

If both the old and the new bitstream configuration files define the same raw data to board ports, the configuration done (refer to section Data to Board) on these ports is kept.

For all common ports, the maximum DWORD count is the lower value among the maximums defined in the two files.

Raw load from board portskeep

If both the old and the new bitstream configuration files define the same raw load from board ports, the configuration done (refer to section Load from Board) on these ports is kept.

For all common ports, the maximum DWORD count is the lower value among the maximums defined in the two files.

Raw load to board portskeep

If both the old and the new bitstream configuration files define the same raw load to board ports, the configuration done (refer to section Load to Board) on these ports is kept.

For all common ports, the maximum DWORD count is the lower value among the maximums defined in the two files.

Remote boards configuration
keepIf the MuSE feature is available in both old and new bitstreams, the remote boards configuration (refer to section Remote Board Configuration) will be kept when loading the new bitstream configuration file.

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  • This driver must be run in Hardware Synchronized mode.
  • Only XHP mode is supported.
  • The disable strict hardware mismatch validation feature is not available on OP5142.
  • Each FPGA must have connections with at least one subsystem running at the model's timestep (in the context of multi-rate subsystems).
  • A configuration having multi-rate subsystems associated with a slave FPGA board does not support the action of Pause/Execute during the simulation.
  • On all chassis, the motor models are not supported for the moment.
  • Chassis type OP5143 standalone is supported only for MuSE as central with four remotes. Using it as MuSE remote is not supported . It does not support any I/Os.
  • For the chassis types OP4810 and OP4815, the maximum support PDI file size is 64 MiB.

List of Compatibilities

Chassis and FPGA boardSupported
OP4500 with an MMPK7 moduleNo longer supported.
OP4510 with a TE0741 moduleYes
OP4512 with a TE0741 module
OP4520 I/O expansion box with a TE0741 module
OP4610 with a TE0741 module
OP5600 with an OP5142 board
OP5600 with an OP5143 board
OP5600 with an ML605 boardNo
OP5607 I/O expansion box with a VC707 boardYes
OP5707 with a VC707 board
OP7020 I/O expansion box with a VC707 board
OP7160/OP7161

No

OP7170Yes
OP5143 standalone PCIe cardYes
OP4810Yes
OP4815Yes

Limitations of the Multi-System Expansion link feature

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Chassis and FPGA boardCentralRemote
OP4500 with an MMPK7 moduleNoNo
OP4510 with a TE0741 moduleYesYes
OP4512 with a TE0741 moduleYes
OP4520 I/O expansion box with a TE0741 moduleYes, if connected via PCIe to a simulator
OP4610 with a TE0741 moduleYes
OP5600 with an OP5142 boardNoNo
OP5650 with an OP5143 boardYesYes
OP5600 with an ML605 boardNoNo
OP5607 I/O expansion box with a VC707 boardYes, if connected via PCIe to a simulatorYes
OP5700 with a VC707 boardYes
OP7020 I/O expansion box with a VC707 boardYes, if connected via PCIe to a simulator
OP7160/OP7161NoNo
OP7170YesYes
OP5143 standaloneYesNo
OP4810NoNo
OP4815NoNo