Description

The current functionality is used to send raw data asynchronously from an RT-LAB model to an OPAL-RT card. This is achieved by using the LoadINports of the FPGA.

As opposed to DataIN, the transfer of LoadIN data is relying on a slower communication link between the FPGA and the CPU and thus is not meant to be used at every step of the simulation. Doing otherwise will lead to decreased simulation performances.

The main purpose of this functionality is to send configuration-type data to the board. The transfer can be done during the load of the RT-LAB model, during the execution of the simulation (with the help of a trigger mechanism) or both. Please check the Usage section below to find the implementation that suits your simulation's needs.

In the RT-XSG implementation, the bitstreams have 32 LoadIN input ports and 32 LoadOUT output ports. Each port has a maximum width of 250 32-bit data words. These ports are used to exchange data asynchronously between the RT-LAB model and the FPGA chip of the card.

Usage

Once the bitstream configuration file has been parsed, the ports capable of asynchronous raw data transfer are revealed to the user.

If the bitstream offers the possibility of transferring raw data asynchronously from the CPU to the FPGA then a new section named Load to board will appear as a subsection of General. There, a dedicated configuration page will be created for each usable port, based on the information parsed from the bitstream configuration file.

The title of each port's configuration page will contain the port number (count starting from 0)and the maximum number of DWORDS serviceable.

By clicking on a port's configuration page, the user can:

• choose the transfer mechanism best suited for the simulation
• choose the data to send to the board (either a .mat file or custom data frames)
• for custom data frames, define the frame format to send

The latter can be achieved by adding, removing and/or moving signals up or down in the data frame table using the buttons found above the table. The configurable parameters of each signal are detailed in the sections below.

Port Configuration

Send .mat Configuration File

When this check-box is selected, a new field will appear, where the user will have to input the path of the .mat file to be transferred to the FPGA.

The transfer of data frames is disabled when this option is selected, therefore the Send configuration data real-time option will become grayed-out.

.mat File Path

The path of the .mat file to transfer to the FPGA.

This parameter is only visible if the Send .mat configuration file check-box is enabled.

Send Configuration Data Real-Time

When this check-box is selected, the interface offers the user the possibility of transferring the data frame during the execution of the simulation, by the means of a trigger mechanism.

Selecting this option will create the connectable points for current port data and trigger in the Configuration panel of the RT-LAB project. It will also cause the Also send configuration initial values field (explained below) to appear.

For the trigger, only a '0' to '1' transition will enable the data transfer. Leaving the value of the trigger at '1' will not allow for data transfer.

When only this option is active, the initial values of signals are disabled since LoadIN data is transferred at run-time. If they require to be transferred during the load of the model as well, then the check-box explained below needs to be activated as well.

Also Send Configuration Initial Values

By checking this box, the initial value parameter of the signals in the data frame is re-enabled and will be sent during the load of the simulation. Once the simulation is executing, data transfer will occur when the trigger's value will pass from '0' to '1' (rising-edge detection).

This field is only visible if the Send configuration data real-time check-box is selected.

If the Send configuration data real-time check-box is selected then adding a signal to the data frame table will also add a connection point for it in the Configuration panel of RT-LAB.

In this scenario, if the table element has a vector size different from 1 (see the section below for a description of the Vector size parameter), then its connectable item in the Configuration panel is an array.

If there is at least one signal to be sent real-time, the trigger connectable point will also be added to the Configuration panel.
For sending data to the FPGA, connections must be made between the points in the model (in the form of OpOutput blocks) and the raw data output connectable points.

In order to achieve that, the connection point for each signal (or array of signals) and each trigger must be drag-and-dropped onto an appropriate OpOutput block in the Configuration panel of the RT-LAB project.

Connections with LabView panels are also possible.

Given all of the above, the transfer scenarios for each port are described below:

Send data only during the load of the model:

• None of the checkboxes have to be enabled
• No connections need to be created
• The initial value of each signal in the data frame table needs to be specified to its required value

Send data at run-time:

• Only the Send configuration data real-time check-box needs to be enabled
• Connections need to be created for each signal (or vector of signals)
• A connection also needs to be created for the port's trigger
• Attention must be paid on how to the trigger is used. Note that starting the simulation with the trigger set to '1' will cause a rising-edge transition to be detected during the first step of the execution. This happens because the interface's connectable point passes from the blank value of '0' to the value received from the model which will be '1' in this scenario.

Send data during the load of the model and at run-time:

• Both the Send configuration data real-time and the Also send configuration initial values check-boxes need to be enabled
• The initial value of each signal in the data frame table needs to be specified to its required value
• Connections need to be created for each signal (or vector of signals)
• A connection also needs to be created for the port's trigger
• Attention must be paid on how to the trigger is used. Note that starting the simulation with the trigger set to '1' will cause a rising-edge transition to be detected during the first step of the execution. This happens because the interface's connectable point passes from the blank value of '0' to the value received from the model which will be '1' in this scenario.

Upload a .mat File

• Only the Send .mat configuration file check-box needs to be enabled
• The file's path needs to be specified in the .mat file path field
• No connections need to be created

Signal Configuration

When not sending .mat files, each signal in the data frame has the following parameters:

Name

The name of the signal (or vector of signals). The name is used if the data is to be transferred during execution as it is the name given to the interface's connectable point.

Type

The type is selectable from a drop-down list. The options are Bit, Unsigned, Signed, Float and Double. They represent how the data will be encoded before being sent to the FPGA.

If the Vector size is greater than 1, then this parameter will be applied to each element of the vector.

Certain types force other parameters to change their value to a fixed one:

• The Bit encoding forces the Size (bits) parameter to 1
• Float forces the Size (bits) parameter to 32 and the Bit offset parameter to 0
• Double forces the Size (bits) parameter to 64 and the Bit offset parameter to 0

Vector Size

Setting this parameter different from 1 will result in the interface creating an array of signals starting at the byte offset specified. Each element of the vector will have the type, size, initial, minimum and maximum values as specified in its table entry. In case the data is to be sent during execution, the name of the connectable created for the vector will be the one specified at the parameter Name.

Using vectors can be beneficial when a data frame has contiguous signals that have the same parameters because it reduces the time necessary to configure the interface. When sending the data real-time, using an array is also more efficient in terms of memory and time-step usage as opposed to using individual connections for each element.

Keeping the value at 1 will maintain the current signal as an individual element of the data frame.

Current constraints are related to vector elements having to be aligned on byte-boundaries:

• The Bit offset parameter cannot be different from 0
• The Size (bits) parameter must be one of the standard data type sizes (i.e. 1, 8, 16, 32 or 64)
• In the case of Type being set to Binary, the maximum vector size is 8

Byte Offset

This parameter represents the byte offset within the load port where the current table element will be written to.

Bit Offset

This parameter represents the bit offset within the byte specified at the Byte offset parameter for the current table element.

The Bit offset cannot be used (i.e. it is grayed out) for Float and Double signal types. It also can't be used in case the table element is a vector (i.e. Vector size is greater than 1).

Size (bits)

The Size (bits) parameter is where the size in bits of the current signal can be specified.

The size is fixed to 1 for Bit types, to 32 for Float types and to 64 for Double types.

The maximum size allowed by the interface is 64 (which is the size of the largest native data type).

If the Vector size is greater than 1, then this parameter will be applied to each element of the vector.

Initial Value

This parameter is only relevant in a scenario where data is sent during the load of the model (either exclusively or combined with sending at run-time).

In other words, the value specified in this field will only be sent to the FPGA during the load of the model.

The value is constrained between the minimum and maximum limits (see items below for a description).

Min

The minimum value that will be sent to the FPGA for this signal. If the Vector size is greater than 1, then this parameter will be applied to each element of the vector.

The value entered for this parameter is limited by the type and size of the signal. As an example, for an 8-bit signed signal, the minimum cannot be less than-128 (the smallest signed integer representable on 8 bits).

For real-time transfers, the current limitation of this parameter is that it is not applicable for Float and Double types.

Max

The maximum value that will be sent to the FPGA for this signal. If the Vector size is greater than 1, then this parameter will be applied to each element of the vector.

The value entered for this parameter is limited by the type and size of the signal. As an example, for an 8-bit signed signal, the maximum cannot be greater than127 (the largest signed integer representable on 8 bits).

For real-time transfers, the current limitation of this parameter is that it is not applicable for Float and Double types.

Characteristics and Limitations

In order to correctly configure the data frames for each port, the user must have knowledge of how the data sent to the ports of interest will be used by the logic implemented in the bitstream.

The current version of the asynchronous raw data output functionality of the OPAL-RT Board driver has the following limitations:

• The bit offset cannot be 0 when the vector size is greater than 1
• The size (in bits) must be standard (i.e. 1, 8, 16, 32, or 64) when the vector size is greater than 1
• The maximum vector size is 8 for the binary data type
• The bit offset cannot be used for any signals of type float or double (i.e. these types of data must be byte-aligned)
• When sending data real-time, the minimum and maximum parameters are not applicable for signals of type float
• When sending data real-time, the minimum and maximum parameters are not applicable for signals of type double