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Load to Board
Description
The current functionality is used to send raw data asynchronously from an RT-LAB model to an OPAL-RT card. This is achieved by using the LoadINports of the FPGA.
As opposed to DataIN, the transfer of LoadIN data is relying on a slower communication link between the FPGA and the CPU and thus is not meant to be used at every step of the simulation. Doing otherwise will lead to decreased simulation performances.
The main purpose of this functionality is to send configuration-type data to the board. The transfer can be done during the load of the RT-LAB model, during the execution of the simulation (with the help of a trigger mechanism) or both. Please check the Usage section below to find the implementation that suits your simulation's needs.
In the RT-XSG implementation, the bitstreams have 32 LoadIN input ports and 32 LoadOUT output ports. Each port has a maximum width of 250 32-bit data words. These ports are used to exchange data asynchronously between the RT-LAB model and the FPGA chip of the card.
Note: Knowledge of the bitstream logic that will use the data sent to the FPGA is necessary for a successful simulation.
Usage
Once the bitstream configuration file has been parsed, the ports capable of asynchronous raw data transfer are revealed to the user.
If the bitstream offers the possibility of transferring raw data asynchronously from the CPU to the FPGA then a new section named Load to board will appear as a subsection of General. There, a dedicated configuration page will be created for each usable port, based on the information parsed from the bitstream configuration file.
The title of each port's configuration page will contain the port number (count starting from 0)and the maximum number of DWORDS serviceable.
By clicking on a port's configuration page, the user can:
- choose the transfer mechanism best suited for the simulation
- choose the data to send to the board (either a .mat file or custom data frames)
- for custom data frames, define the frame format to send
The latter can be achieved by adding, removing and/or moving signals up or down in the data frame table using the buttons found above the table. The configurable parameters of each signal are detailed in the sections below.
Port Configuration
Send .mat Configuration File
When this check-box is selected, a new field will appear, where the user will have to input the path of the .mat file to be transferred to the FPGA.
The transfer of data frames is disabled when this option is selected, therefore the Send configuration data real-time option will become grayed-out.
MAT-File supported format is version 4. Matrix must be stored as double value which is a requirement of the version 4 of the file. These values will be converted to unsigned integer 32 bits before being sent to the FPGA.
Only one matrix is usable in the MAT-File, subsequent ones will be ignored.
Matrix will be sent line by line. A start of frame signal will be sent before each line.
.mat File Path
The path of the .mat file to transfer to the FPGA.
This parameter is only visible if the Send .mat configuration file check-box is enabled.
Send Configuration Data Real-Time
When this check-box is selected, the interface offers the user the possibility of transferring the data frame during the execution of the simulation, by the means of a trigger mechanism.
Selecting this option will create the connectable points for current port data and trigger in the Configuration panel of the RT-LAB project. It will also cause the Also send configuration initial values field (explained below) to appear.
For the trigger, only a '0' to '1' transition will enable the data transfer. Leaving the value of the trigger at '1' will not allow for data transfer.
When only this option is active, the initial values of signals are disabled since LoadIN data is transferred at run-time. If they require to be transferred during the load of the model as well, then the check-box explained below needs to be activated as well.
Also Send Configuration Initial Values
By checking this box, the initial value parameter of the signals in the data frame is re-enabled and will be sent during the load of the simulation. Once the simulation is executing, data transfer will occur when the trigger's value will pass from '0' to '1' (rising-edge detection).
This field is only visible if the Send configuration data real-time check-box is selected.
If the Send configuration data real-time check-box is selected then adding a signal to the data frame table will also add a connection point for it in the Configuration panel of RT-LAB.
In this scenario, if the table element has a vector size different from 1 (see the section below for a description of the Vector size parameter), then its connectable item in the Configuration panel is an array.
If there is at least one signal to be sent real-time, the trigger connectable point will also be added to the Configuration panel.
For sending data to the FPGA, connections must be made between the points in the model (in the form of OpOutput blocks) and the raw data output connectable points.
In order to achieve that, the connection point for each signal (or array of signals) and each trigger must be drag-and-dropped onto an appropriate OpOutput block in the Configuration panel of the RT-LAB project.
To create a connection, either for a signal or array, to the appropriate OpOutput block, use the Dashboards interface, accessible from the project, and refer to its documentation.
Connections with Dashboards panels are also possible.
Given all of the above, the transfer scenarios for each port are described below:
Send data only during the load of the model:
- None of the checkboxes have to be enabled
- No connections need to be created
- The initial value of each signal in the data frame table needs to be specified to its required value
Send data at run-time:
- Only the Send configuration data real-time check-box needs to be enabled
- Connections need to be created for each signal (or vector