Description

The current functionality retrieves the raw data from an OPAL-RT card at each time step. This is achieved using the DataOUT ports of the FPGA.

It is meant for situations when the DataOUT ports are not directly connected to IO packing blocks.

In the RT-XSG implementation, the bitstreams have 32 DataIN input ports and 32 DataOUT output ports. Each port has a maximum width of 250 32-bit data words. These ports exchange data between the RT-LAB model and the FPGA chip of the card.

Note: Knowledge of the bitstream logic generating the data sent through the DataOUT ports is necessary for a successful simulation.

Usage

Once the bitstream configuration file has been parsed, the ports capable of raw data transfer are revealed to the user.

If the bitstream offers the possibility of transferring raw data from the FPGA to the CPU then a new section named Data from the board appears as a subsection of General.

There, a dedicated configuration page is created for each usable port, based on the information parsed from the bitstream configuration file. The title of each port's configuration page contains the port number (counted starting from 0) and the maximum number of DWORDS serviceable.

By clicking on a port's configuration page, the user can create the data frame format expected from the FPGA. This can be achieved by adding, removing and/or moving signals up or down in the data frame table using the buttons found above the table. The configurable parameters of signals are detailed in the section below.

Adding a signal to the data frame table also adds a connection point for it in the Configuration panel of RT-LAB.

If the table element has a vector size different from 1 (see the section below for a description of the Vector size parameter), then its connectable item in the Configuration panel is an array.

For displaying and/or monitoring the data received from the FPGA, connections must be made between the points in the model (in the form of OpInput blocks) and the raw data input connectable points.

To do this, the connection point for each signal (or array of signals) must be drag-and-dropped onto an appropriate OpInput block in the Configuration panel of the RT-LAB project.

Connections with LabView panels are also possible.

Signal configuration

Name

The name of the signal (or vector of signals) is important as it is the name given to the interface's connectable point.

Type

The type is selectable from a drop-down list. The options are Bit, Unsigned, Signed, Float and Double. They represent the encoding to be used when interpreting data received from the FPGA.

If the Vector size is greater than 1, this parameter is applied to each element of the vector.

Certain types force other parameters to change their value to a fixed one:

The Bit encoding forces the Size (bits) parameter to 1
Float forces the Size (bits) parameter to 32 and the Bit offset parameter to 0
Double forces the Size (bits) parameter to 64 and the Bit offset parameter to 0

Vector Size

Setting this parameter different from 1 will result in the interface creating an array of signals starting at the byte offset specified. Each element of the vector will have the type, size, minimum and maximum values as specified in its table entry. The name of the connectable created for the vector will be the one specified at the parameter Name.

Using vectors can be beneficial when a data frame has contiguous signals that have the same parameters because it reduces the time necessary to configure the interface.
Keeping the value at 1 will maintain the current signal as an individual element of the data frame.

Current constraints are related to vector elements having to be aligned on byte-boundaries:

The Bit offset parameter cannot be different from 0
The Size (bits) parameter must be one of the standard data type sizes (i.e. 1, 8, 16, 32 or 64)
In the case of Type being set to Binary, the maximum vector size is 8

Byte Offset

This parameter represents the byte offset within the data port where the current table element will be read.

Note: The interface can check for data overlap: to check that the configuration is valid, the user clicks the check-mark found next to the subsystem association drop-down, in the interface's view.

Bit Offset

This parameter represents the bit offset within the byte specified at the Byte offset parameter for the current table element.

Note: The interface can check for data overlap: to check that the configuration is valid, the user clicks on the check-mark icon found next to the subsystem association drop-down, in the interface's view.

The Bit offset cannot be used (i.e. it is grayed out) for Float and Double signal types. It also can't be used in case the table element is a vector (i.e. Vector size is greater than 1).

Size (bits)

The Size (bits) parameter is where the size in bits of the current signal can be specified.

The size is fixed to 1 for Bit types, to 32 for Float types and to 64 for Double types.

The maximum size allowed by the interface is 64 (which is the size of the largest native data type).

If the Vector size is greater than 1, then this parameter will be applied to each element of the vector.

Note: The interface can check for data overlap: to check that the configuration is valid, the user clicks on the check-mark icon found next to the subsystem association drop-down, in the interface's view.

Min

The minimum value to be reported in the Simulink model or LabView panel for this signal. If the Vector size is greater than 1, then this parameter is applied to each element of the vector.

Note: The value given by the FPGA may be lower than the minimum. In this case, the interface reports the minimum.

The value entered for this parameter is limited by the type and size of the signal. As an example, for an 8-bit signed signal, the minimum cannot be less than-128 (the smallest signed integer representable on 8 bits).

The current limitation of this parameter is that it is not applicable for Float and Double types.

Max

The maximum value to be reported in the Simulink model or LabView panel for this signal. If the Vector size is greater than 1, then this parameter is applied to each element of the vector.

Note: The value given by the FPGA may be greater than the maximum. In this case, the interface reports the maximum.

The value entered for this parameter is limited by the type and size of the signal. As an example, for an 8-bit signed signal, the maximum cannot be greater than 127 (the largest signed integer representable on 8 bits).

The current limitation of this parameter is that it is not applicable for Float and Double types.

Characteristics and Limitations

In order to correctly configure the data frames for each port, the user must have knowledge of how data on the ports of interest is generated by the logic implemented in the bitstream.

The current version of the raw data input functionality of the OPAL-RT Board driver has the following limitations:

The bit offset cannot be 0 when the vector size is greater than 1
The size (in bits) must be standard (i.e. 1, 8, 16, 32 or 64) when the vector size is greater than 1
The maximum vector size is 8 for the binary data type
The bit offset cannot be used for any signals of type float or double (i.e. these types of data must be byte-aligned)
The minimum and maximum parameters are not applicable for signals of type float
The minimum and maximum parameters are not applicable for signals of type double

RT-LAB Documentation

Data from Board