Description

The Analog Out functionality of the OPAL-RT Board driver provides the simulation with the possibility of outputting analog voltage values through the analog output channels of the OP5330 modules installed in the simulator.

The data values are transferred from the simulation through the DataIN ports of the FPGA.

The data port numbers and the location of the analog output modules in the simulator are specified in the bitstream configuration file, which must be provided in the General section of the configuration of the OPAL-RT Board driver.

Once the driver has read the bitstream configuration file, the user can see the location of the analog output modules and can configure them.

The OPAL-RT Board driver can control all of the analog output modules of the simulator at the same time. Therefore, the maximum number of analog output channels is limited by the hardware configuration of the simulator in use.

Usage

This section describes the usage of the classic analog out functionality of the simulator. For the resolver out functionality that makes use of the analog output modules of the simulator, see the Resolver Out documentation.

Once the bitstream configuration file has been parsed, the location of the analog output modules becomes visible to the user. The channels of the modules are grouped into bunches of 8. By clicking each group of 8, the user has access to the configurable options of the group.

While physically there is only one kind of analog output module, there are two possible logic modules controlling it in the bitstream.

• The first one is a standard analog output module, that takes the data from the simulation and packages it in the way required by the physical module.
• The second one is called the Advanced Analog Out module and it offers the feature of doing extra processing for each analog output channel before packaging it.
• More details on the processing options can be found in the Signals Configuration section below.

Additionally, the Advanced Analog Out offers the user the possibility of selecting the source of data for each channel. The sources can be either from the simulation (from the Simulink model or LabView panels) or from other blocks internal to the bitstream (such as electric solvers).

Bitstream files generated with an RT-XSG version of 3.1.2 or later offer the possibility of using the Advanced Analog Out feature.

The user knows if the bitstream is equipped with Advanced Analog Out as soon as its configuration file is loaded in the General section of the OPAL-RT Board configuration page.

If only standard analog output is supported, then no processing options can be seen in the signals list (it will only be a list with channel names), whereas if the Advanced Analog Out is supported, then the above-mentioned options are visible and configurable.

Slot Configuration

Voltage Range

This drop-down menu allows the user to choose the voltage range to be used by the analog out slot. The options are -16 V/+ 16 V, -10 V/+ 10 V and -5 V/+ 5 V. The voltage range is applied to all 16 channels of the physical module.
Negative values out of range are saturated to the range's lower limit before being sent to the IO card; conversely, positive out of range values are saturated to the upper limit of the range.

The 16-bit resolution for the D/A is maintained when you select any of the three voltage range available. In other words, if the -10 V/+ 10 V range is selected for instance, then, the 16-bit resolution will be on a range of 20V.

Channel Group Configuration

Enable

Checking this box will enable the transmission of analog data for the channels in the group once the simulation has started.

Clicking on Enable also adds the group of channels as connectable in the Configuration panel of RT-LAB. For the standard analog output modules, the channels will appear as a contiguous connectable vector. Otherwise, for the Advanced Analog Out modules, they will appear as individual connectable items. The reason for this difference is that the sources of the Advanced Analog Out channels may not all be from RT-LAB.

Take the following example:

In the case of the above example, the sources of channels 2 and 4 are the outputs of the logic block named eHS (which is an Opal-RT electric solver running in the FPGA)found in the bitstream. This means that these two channels do not require to communicate with RT-LAB. As a result, they will not be added to the connectable points tree while the other 6 channels will.

In order to output data from the model, connections must be made between points in the model (in the form of OpOutput blocks) and the analog output connectable points.

To create a connection, the user has to drag-and-drop the connectable items (either vector or individual channel) onto an appropriate OpOutput block in the Configuration panel of the RT-LAB project.

In the case of the standard analog output, a connection can be made either on the entire vector or on each individual item of the vector (i.e. analog output channel).

Connections with LabView panels are also possible.

Signals Configuration

Channels in analog output groups that were identified as standard do not have any parameters to configure.

Channels in analog output groups that were identified as Advanced Analog Out have the following parameters to configure:

Signal Source

This parameter allows the user to choose the source of data for each of the analog output channels in the group. It is presented as a drop-down list and the choices present in this list are determined by what logic blocks are available in the bitstream and which one of those are activated.

Therefore, the signal source of each analog output channel can be:

• The CPU (i.e. sending data from the Simulink model or LabView panels)
• Data coming from the logic that is internal to the FPGA. As in the example above, the choices could be outputs of an eHS block

Characteristics and Limitations

For the connector pin assignments, the user should refer to the carrier documentation.

The current version of the analog output functionality of the OPAL-RT Board driver has the following limitations:

• Limitations will be added as they are found