| Title: | Building Models with RT-XSG | |
|---|---|---|
| Owner: | Sylvain Ménard | |
| Creator: | Sylvain Ménard | Mar 11, 2023 |
| Last Changed by: | Sylvain Ménard | Mar 11, 2023 |
| Tiny Link: (useful for email) | https://opal-rt.atlassian.net/wiki/x/z1ycC | |
| Export As: | Word · PDF | |
Hierarchy
Children (8)
System Generator for DSP Toolbox Gateway and Mandatory Blocks
Augmented Dword 33 Bit Data Vectors
Creating CONF File for an RT-XSG Design
Inserting Custom VHDL Files into a Model
Offline Simulation
Bitstream Generation and FPGA Configuration
Building an RT-LAB Compatible RT-XSG Model
Creating IOCONF File for an RT-XSG Design
System Generator for DSP Toolbox Gateway and Mandatory Blocks
Augmented Dword 33 Bit Data Vectors
Creating CONF File for an RT-XSG Design
Inserting Custom VHDL Files into a Model
Offline Simulation
Bitstream Generation and FPGA Configuration
Building an RT-LAB Compatible RT-XSG Model
Creating IOCONF File for an RT-XSG Design
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