Analog Outputs

Description
The Analog Out functionality of the OPAL-RT Board driver provides the simulation the possibility of outputting analog voltage values through the analog output channels of the OP5330 modules installed in the simulator.
In the case of the OP4200 chassis, the OP5330 module is incorporated into the I/O cassette with ID OP4230-1.
The data values are transferred from the simulation through the DataIN ports of the FPGA.
The data port numbers and the location of the analog output modules in the simulator are specified in the bitstream configuration file, which must be provided in the main section of the current board's configuration.
Once the driver has read the bitstream configuration file, the user can see the location of the analog output modules and can configure them.
The OPAL-RT Board driver can control all of the analog output modules of the simulator at the same time. Therefore, the maximum number of analog output channels is limited by the hardware configuration of the simulator in use.
Usage
This section describes the usage of the classic analog out functionality of the simulator. For the resolver out functionality that makes use of the analog output modules of the simulator, please see the Resolver Outputs documentation.
Once the bitstream configuration file has been parsed, the location of the analog output modules becomes visible to the user. The channels of the modules are grouped into bunches of 8. By clicking on each group of 8, the user has access to the configurable options of the group.
While physically there is only one kind of analog output module, there are two possible logic modules controlling it in the bitstream. The first one is a standard analog output module, that takes the data from the simulation and packages it in the way required by the physical module.
The second one is called the Advanced Analog Out module and it offers the feature of doing extra processing for each analog output channel before packaging it. More details on the processing options can be found in the Signals configuration section below.
Moreover, the Advanced Analog Out offers the user the possibility of selecting the source of data for each channel. The sources can be either from the simulation or from other blocks internal to the bitstream (such as electric solvers).
Bitstream files generated with an RT-XSG version of 3.1.2 or later offer the possibility of using the Advanced Analog Out feature.
The user will know if the bitstream is equipped with Advanced Analog Out as soon as the bitstream configuration file is loaded in the main section of the current board's configuration page.
If the bitstream only supports standard analog output then no processing options can be seen in the signals list (it will only be a list with channel names), whereas if the Advanced Analog Out is supported, then the above mentioned options will be visible and configurable.
Slot configuration
Apart from the default fields of a slot configuration (described in the overview help document of the OPAL-RT Board driver), the following field can also be configured:
Voltage range
This drop-down menu allows the user to choose the voltage range to be used by the analog out slot. The options are -16 V / + 16 V, -10 V / + 10 V or -5 V / + 5 V. The voltage range will be applied to all 16 channels of the physical module.
Negative out of range values are saturated to the range's lower limit before being sent to the IO card; conversely, positive out of range values are saturated to the upper limit of the range.
Channel group configuration
Name The name of the channel group denotes the physical channels of the analog output module the current configuration will be applied to.
Enable Checking this box will enable the transmission of analog data for the channels in the group once the simulation has started.
Clicking on Enable also makes the group of 8 channels available as connections in HYPERSIM .
Signals configuration
Channels in analog output groups that were identified as standard do not have any parameters to configure.
Channels in analog output groups that were identified as Advanced Analog Out have the following parameters to configure:
Signal source
This parameter allows the user to choose the source of data for each of the analog output channels in the group. Is it presented as a drop-down list and the choices present in this list are determined by what logic blocks are available in the bitstream and which one of those are activated.
Therefore, the signal source of each analog output channel can be:
The CPU (i.e. sending data from the model)
Data coming from logic that is internal to the FPGA. Take the following example:
source of channel 0 CPU (HYPERSIM)
source of channel 1 CPU (HYPERSIM)
source of channel 2 logic_block_src1
source of channel 3 CPU (HYPERSIM)
source of channel 4 logic_block_src2
source of channel 5 CPU (HYPERSIM)
source of channel 6 CPU (HYPERSIM)
source of channel 7 CPU (HYPERSIM)
In the case of the above example, the sources of channels 2 and 4 are the outputs of a logic block named "logic_block" found in the bitstream. This means that these two channels do not require to communicate with HYPERSIM . As a result, they will not be added to the driver's connectable points list while the other 6 channels will.
Gain The value entered for the gain parameter will be multiplied with the analog signal before it being outputted on the physical module.
The gain of each signal will be applied in the FPGA. Therefore, this operation does not add any computation time for the model.
Any floating point values are considered valid for this field. Example: Aout = Gain * Data + Offset
Offset The value entered for the offset parameter will be added to the analog signal before it being outputted on the physical module.
The offset of each signal will be applied in the FPGA. Therefore, this operation does not add any computation time for the model.
Any floating point values are considered valid for this field.
Minimum The value entered for the minimum parameter will be used as a low-limit cut-off of the analog signal before it being outputted on the physical module.
The minimum of each signal will be applied in the FPGA. Therefore, this operation does not add any computation time for the model.
Values accepted for this field are any floating point values equal to or greater than the lower limit of the selected voltage range (i.e. -16, -10 or -5 V) but not more than the value denoted by the maximum limit (item below).
Maximum The value entered for the maximum parameter will be used as an upper-limit cut-off of the analog signal before it being outputted on the physical module.
The maximum of each signal will be applied in the FPGA. Therefore, this operation does not add any computation time for the model.
Values accepted for this field are any floating point values equal to or lower than the upper limit of the selected voltage range (i.e. 16, 10 or 5 V) but not less than the lower limit (item above).

Characteristics and Limitations
For the connector pin assignments, the user should refer to the carrier documentation.

The current version of the analog output functionality of the OPAL-RT Board driver has the following limitations:
Limitations will be added as they are found

Name	The name of the channel group denotes the physical channels of the analog output module the current configuration will be applied to.
Enable	Checking this box will enable the transmission of analog data for the channels in the group once the simulation has started. Clicking on Enable also makes the group of 8 channels available as connections in HYPERSIM .

source of channel 0	CPU (HYPERSIM)
source of channel 1	CPU (HYPERSIM)
source of channel 2	logic_block_src1
source of channel 3	CPU (HYPERSIM)
source of channel 4	logic_block_src2
source of channel 5	CPU (HYPERSIM)
source of channel 6	CPU (HYPERSIM)
source of channel 7	CPU (HYPERSIM)

Gain	The value entered for the gain parameter will be multiplied with the analog signal before it being outputted on the physical module. The gain of each signal will be applied in the FPGA. Therefore, this operation does not add any computation time for the model. Any floating point values are considered valid for this field. Example: Aout = Gain * Data + Offset
Offset	The value entered for the offset parameter will be added to the analog signal before it being outputted on the physical module. The offset of each signal will be applied in the FPGA. Therefore, this operation does not add any computation time for the model. Any floating point values are considered valid for this field.
Minimum	The value entered for the minimum parameter will be used as a low-limit cut-off of the analog signal before it being outputted on the physical module. The minimum of each signal will be applied in the FPGA. Therefore, this operation does not add any computation time for the model. Values accepted for this field are any floating point values equal to or greater than the lower limit of the selected voltage range (i.e. -16, -10 or -5 V) but not more than the value denoted by the maximum limit (item below).
Maximum	The value entered for the maximum parameter will be used as an upper-limit cut-off of the analog signal before it being outputted on the physical module. The maximum of each signal will be applied in the FPGA. Therefore, this operation does not add any computation time for the model. Values accepted for this field are any floating point values equal to or lower than the upper limit of the selected voltage range (i.e. 16, 10 or 5 V) but not less than the lower limit (item above).