Description

The Resolver Out functionality of the OPAL-RT Board driver provides the simulation the possibility of outputting resolver signals through the analog output channels of the OP5330 modules installed in the simulator.
In the case of the OP4200 chassis, the OP5330 module is incorporated into the I/O cassette with ID OP4230-1.

The functionality is based on the basic two-pole resolver. There are two resolvers implemented in each subgroup of 8 analog out channels.
The user has the possibility to choose if the carrier wave of a resolver is generated internally by the FPGA or if it is received from an external device.
Furthermore, the speed and the sine and cosine wave parameters (amplitude and offset) can be changed during the simulation for each resolver. If the carrier wave is generated internally, the user can also control the wave's amplitude and frequency. 

For each of the parameters controllable at run-time described above there is a connection point provided.

• The Speed is represented in Hertz (Hz) and can be positive or negative to represent forward or backward movement. Therefore, its limits are between -20000 to 20000 Hz.
• The Carrier Amplitude (if carrier is generated internally), Sine Amplitude and Cosine Amplitude are represented in Volts and have ranges from 0 to 16 V.
• Sine Offset and Cosine Offset are also represented in Volts and have a range of -16 V to 16 V.
• Finally, for internally generated carriers, the Carrier Frequency is represented in Hertz and is limited between 0 and 95000 Hz.

Usage

Once the bitstream configuration file has been parsed, the location of the analog output modules becomes visible to the user. The channels of the modules are grouped into bunches of 8. By clicking on each group of 8, the user has access to the configurable options of the group.

Channel group configuration

• Name
  The name of the channel group denotes the physical channels of the analog output module the current configuration will be applied to.
  
  
• Enable
  Checking this box will enable the generation of resolver data for the channels in the group once the simulation has started, provided that the type of functionality is set to Resolver Out (see item below for more detail).
  Clicking on Enable also makes each resolver's (2 resolvers per subgroup) connection points available in HYPERSIM. In order to output data, connections must be made between points in the model and the resolver output connectable points.
  
  
• Type
  This grayed-out field has the purpose of displaying to the user the functionality of the current channel subgroup. For the sending of resolver data, please verify that the field displays Resolver Out.
  
  
• Carrier 1 select mode
  Select which carrier wave to use for generating the resolver signals. This parameter will be applied to the first resolver in the subgroup. The options are: 

• • Internal, meaning the carrier wave will be generated internally by the FPGA. In this case, the user will have the option of controlling the amplitude and the frequency of the wave at run-time through the functionality's connections points.
    Therefore, selecting Internal will make the Carrier Amplitude and Carrier Frequency connection points available to use in HYPERSIM.
    
    
  • External, meaning that the carrier wave will be received from an external device.
    Selecting External will remove the Carrier Amplitude and Carrier Frequency connection points from HYPERSIM.
  
  
• Carrier 2 select mode
  Same as above, the parameter being applied to the second resolver of the subgroup. 

Signals configuration

Channels in resolver output groups do not have any parameters to configure.
The table below shows how the resolver outputs translate to the physical channels of the analog output module.

In order for the resolver to function correctly when configured to expect an external carrier wave, the user designing the bitstream must take care of which analog input channel is used by the Resolver Out functionality. This will be important when the equipment generating the wave will be connected to the analog input modules of the simulator.

In most bitstreams containing resolvers provided by Opal-RT, both the input and the output functionalities are present. Therefore, in most cases, the external carrier wave for the first Resolver Out of a subgroup is the fourth analog input channel (channel 3 or 11, depending on the subgroup); for the second Resolver Out of the subgroup, it is the eighth analog input channel (channel 7 or 15, depending on the subgroup).

If there are any doubts about how the signals are routed, please consult the RT-XSG model used to generate the programmable bitstream file. If the model is not available, please contact Opal-RT support.

Characteristics and limitations

For the connector pin assignments, the user should refer to the carrier documentation.

The current version of the resolver analog output functionality of the OPAL-RT Board driver has the following limitations:

• The speed supported is between -20000 Hz and 20000 Hz
• The carrier frequency is between 0 Hz and 95000 Hz
• The product of the carrier's and sine wave's amplitudes must not be more than 16 V; this is due to hardware limitations
• The product of the carrier's and cosine wave's amplitudes must not be more than 16 V; this is due to hardware limitations