Board Architecture
The input/output conditioning is managed by the Type B /wiki/spaces/OP5367/pages/29360437module.
A CPLD is used to configure the fault insertion unit (FIU) section and the OP5367. It is responsible for the communication of the SLSC card within the NI environment for identification, error reporting, etc. It also receives configuration from the software and applies it to the FIU and to some of the I/Os.
The FIU specification and topology are common to all OP8900 boards.
General | |
|---|---|
Product Name | 32 Channels High Range DIO |
Part Numbers | |
Board Type | Digital input/output conditioning |
Form Factor | SLSC |
SLSC Module Design Specifications | Version 1.2.1 |
SLSC Compliance Level | 1 |
Rear I/O Compatibility | [01] (Digital Input/Output up to 32 channels) |
Hot-Plug support | no |
Characteristic | |
Number of Channels | 32 IO in 4 Banks configurable as inputs or outputs Bank1 : D0-7 Bank2 : D8-15 Bank3 D16-23 Bank4 D24-31 |
Input direction | |
Input Impedance | > 100 K Ohm |
Reverse voltage protection | Signal diode |
Maximum voltage protection | +/- 50 V |
Detection threshold | 4 programmable Schmitt Trigger Level step .1176V from .470v to 29.4 Threshold high and Threshold Low for each bank |
Recommended levels threshold | The default thresholds are: LOW level = 1.5V HIGH Level = 3.5V To improve noise immunity, a LOW-level Threshold of 1/3 Vuser, and a HIGH-level Threshold of 2/3 Vuser, are recommended. |
Voltage Range | 0 to 30 Vdc |
Delay Low-to-High | 10ns (implementation-dependent) |
Delay High-to-Low | 15ns (implementation-dependent) |
Output Direction | |
Output Protection | 50 mA resettable fuse |
Output impedance | 2 to 15 ohm |
Protection thresholds | Maximum Vuser + 0.5V Minimum -0.5V |
Output voltage range | 4.5 to 24V Max ( default internal 4.5V) |
Logic high levels ( typical) | Vuser <= 25v , noload : Vuser -0.2V 50mA : Vuser -0.8V Vuser > 25v , noload : Vuser -3.5V 50mA : Vuser -4.7V |
Logic Low levels ( typical) | Vuser 5V to 30V V low= 0.1V |
Delay Low-to-high ( hardware typical * ) | < 100ns @25c for 25V < 90ns @25c for 5V |
Delay High-to-Low ( hardware typical * ) | < 100ns @25c for 25V < 90ns @5c for 5V |
Rise / Fall time ( x to Y) | < 20 ns @ 5V < 50ns @ 30V |
Minimum Pulse detection (resolution) | 90 ns @ 5V 130ns 30V |
Output Frequency | DC to 8 Mbit (1) |
Environmental | |
Important | Designed for indoor use only. |
Storage temperature | -40 °C to 85 °C |
Operating humidity | 10% to 90% non-condensing |
Storage humidity | 5% to 95% non-condensing |
Pollution Degree | 2 |
Maximum altitude | 2,000 m |
Power requirement | 21W |
Number of clock outputs simulated (power limitation) | |||||
|---|---|---|---|---|---|
Frequency/Vuser | 5V | 10V | 15V | 22V | 30V |
< 500 Kb | 32 | 32 | 32 | 32 | 32 |
1 Mb | 32 | 32 | 32 | 24 | 18 |
2 Mb | 32 | 32 | 24 | 14 | 12 |
4 Mb | 32 | 24 | 16 | 8 | 5 |
8 Mb | 24 | 16 | 12 | 5 | 4 |