Description

This block controls a FPGA-based one-phase discrete Phase-Lock Loop. It includes a configurable PID controller, a second-order filter and a rate limiter.

Mask Parameters

Initial frequency: This parameter sets the initial frequency in the PID regulator as well as in the frequency filter state variables.

PID regulator coefficients [ Kp Ki Kd ]: This parameter sets the PID regulator coefficients.

Frequency filter cut-off frequency: This parameter sets the cut-off frequency of the second-order filter applied on the PID outputs to regulate the estimated frequency.

Frequency filter damping factor Zeta: This parameter sets the Zeta damping parameter of the second-order filter applied on the PID outputs to regulate the estimated frequency.

Frequency filter maximum slew rate: This parameter sets the maximum slew rate in input of the second-order filter, as applied to the output of the PID regulator.

Frequency dynamic range: This parameter sets the dynamic range of the reachable estimated frequency, as a saturation parameter for the PID regulator.

Controller Name: Binds this block to an OpCtrl block by entering the same 'Controller Name' as specified in the OpCtrl block The OpCtrl block controls initialization of the settings of one specific card in the system.

LoadIn port number for PID Regulator: This parameter should reflect the communication port used to send parametrization data to the PID Regulator. Refer to the firmware documentation to know how to set this parameter.

LoadIn port number for Second-Order Filter: This parameter should reflect the communication port used to send parametrization data to the Second-Order Filter. Refer to the firmware documentation to know how to set this parameter.

LoadIn port number for Discrete Rate Limiter: This parameter should reflect the communication port used to send parametrization data to the Discrete Rate Limiter. Refer to the firmware documentation to know how to set this parameter.

DataOut port number for Angle feedback: This parameter should reflect the communication port used to receive the estimated Angle feedback from the PLL. Refer to the firmware documentation to know how to set this parameter.

DataOut port number for Frequency feedback: This parameter should reflect the communication port used to receive the estimated Frequency feedback from the PLL. Refer to the firmware documentation to know how to set this parameter.

Inputs

This block has no input.

Outputs

Theta: This output is the output phase of the PLL.

Frequency: This output is the output frequency of the PLL.

Characteristics and limitations

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