Description

This block processes the communication between the RT-Lab model and the FPGA motor model. It also initialises the FPGA motor solver with the user motor definition file.
It supports multiple file types:

• JSOL JMAG v10.5 rtt files
• Infolytica MotorSolve mat files
• ANSYS Maxwell mat files

Mask Parameters

GENERAL TAB Tab

Solver Step Time: Step time in seconds of the FPGA PMSM solver step time. This parameter must be between 400ns and 4us and a multiple of 50ns.

Block Index: This value is used to index initialization data when the same solver is used several times in the FPGA. For example, to make sure that subsystem A does not receive data from subsystem B. This value must be between 0 and 15.

Number of Motors Enable: This parameter activates the 2nd motor or optimizes the solver for use by only one motor. When only one motor is used, the memory that would have been used for the 2nd motor's inductance/flux and torque tables will be used to improve the tables for motor 1. Motor 2 is therefore disabled.

Data In/Load In/Data Out port number:Number of communication ports from/to FPGA to send/receive solver data. Port numbers depend on the bitstream (See bitstream technical documentation to know the right port numbers). If your bitstream was modified, consult its technical note for the port numbers associated to the dual PMSM motors SH block.

Controller Name: FPGA controller name that refers to the motor model bitstream (in OpCtrl or Oplnk block. Usually 'OpCtrl'.).

MOTOR 1&2 TABS

Motor Type: "JMAG 10.5 PMSM Spatial Harmonics rtt file", "Infolytica PMSM Spatial Harmonics mat file" or "Ansys PMSM Spatial Harmonics mat file". This option let you choose the kind of data you want to use to define your motor. The files are generated by JSOL JMAG, Infolytica Motorsolve or Ansys Maxwell softwares. The "Dual PMSM Motors SH" supports only 3 phase PMSM WYE connected motor designs. File supported are JMAG *.rtt files and Ansys or Infolytica *.mat or *.json files.

Rtt/Mat file Path: Path of your Rtt/Mat/json file. You must encapsulate the path name between single quotes or your file will not be found.

Park transform for Id Iq scaling: Depending on the park transform you use the Id Iq monitoring signals might not be well scaled. This parameter is used to rescale the Id Iq / Vd Vq signals in RT-Lab model with the right gain factor. You have the choice between the quadrature transform (with sqrt(2/3) factor) and the original Park-Clarke transform (with (2/3) factor). This parameter does not change the scaling of Id Iq signals available in the FPGA which can be mapped on Aout. By default the park transform use in the FPGA is the quadrature transform.

Rotor Flux position when theta = 0: This parameter allow you to choose to have q axis on the A axis when theta = 0 (modified park) or d axis on the A axis when theta = 0. This will set the FPGA dq transform in the right referential. You can also manually change the angle offset.

Vabc filter cut-off Frequency: [Hz] There is an embedded filter in the motor solver to help the user to visualise the Vabc voltage. Because the original traces are square like, it is very hard to figure out the trace of Vabc. This tools simulate an RC filter on Vabc. The gain is force to 1, but the cut-off frequency can be easily tuned. This value must be between 0.01 and 10 kHz. For a good result, the value has to be more than twice the electrical motor speed (in Hz) and less than half the PWM frequency.

Use advance table settings: This checkbox allow the user to set its own table settings. By default 16 levels for Iamp axis, 32 levels for theta axis and 32 levels for beta axis are used.
Each number of levels has to be a power of 2. Furthermore, the system is limited to 14bits tables while using 2 motors and 15bits with 1 motor enable.
To know the number of bit you are using, you have to add the log2 value of the levels number along all axes. For example in the case above: log2 (16) + log2 (64) + log2 (32) = 4 + 6 + 5 = 15bits. This table configuration would only work in one motor mode.

Delay Motor 1 - Motor 2 (fpga clk number) (Motor 2 tab only)
This parameter lets the user setup the 2 motors calculation delay. The minimum value is 40 and the maximum value is (solver step time)/5e-9 - 40. This parameter is unused for single motor configuration. It could be help full to assure the same inverter - motor coupling delays on both motors.
For example if the inverter runs at 150ns, a good tuning would be to set the motor step time to 450ns (3times the inverter step time) and the delay between motor 1 and 2 computation at 60 (300ns). So both motors simulations start at the beginning of an inverter simulation step and never drift regarding the inverter period.

Inputs

Motor#MecSpeedRPM: Mechanical speed of the motor in RPM. The natural limit of this value is 366000 RPM. The resolution is 1.7e-4 RPM. Depending on the motor topologies this could be an unrealistic limit. If the input goes over the limit, the value sent to the FPGA will be the nearest correct value.

Rst: Reset of the FPGA motor solver. This action will result to a reset of all motors' current states to 0. This is a double signal. The reset is active when input is higher than 0.5.

Advanceport#: This port provides an access to advance solver request. You have to use the "SH_motor_AdvanceCmd" block in tools lib to access its functionality. With the SH model, this port allow the user to update the Rabc values, force the angle to a position or change the cut-off frequency.

You can only change one parameter at a time. The priority is define this way:
Rabc mot1 > Rabc mot2 > Theta mot1 > Theta mot2 > Vabc cut-off freq mot1 > Vabc cut-off freq mot2
Those parameters are slow to update. The modification of these parameters is not made to be real time. Overruns can occur while using this functionality.

Outputs

Motor#signals: These signals are the motor monitoring signals from the FPGA. Please see the list below to have an overview of the available signals:

Signal List:

• Ia/Ib/Ic
• Vn (currently unsupported)
• Idq
• Theta Mec/Elec
• Torque
• RPM_speed
• Vabc_filtered
• Vdq

Characteristics and limitations

Offline simulation: This block is not capable of offline simulation.

Communication delays: The block latency is 2 CPU Time steps.

If you require more information, please contact https://www.opal-rt.com/contact-technical-support/.