Description

This block filters the data stream from an init bus signal and provides the data, address and write enable ports to connect to a Xilinx Ram block. It is used to write a LUT content on the FPGA or a list of parameter in FPGA Ram instance (as shown in the block picture above ).

Mask Parameters

RAM Param ID filter value: This parameter sets the Param ID value to be filtered. Only the frame with the right param id will be filtered.

RAM Data width: Width in number of bits of the data to be written in the RAM (between 1 and 32).

RAM Address width:Width in number of bits of the address bit vector of the RAM. This defines the memory depth of the RAM (depth = 2^number of bit of the address), meaning the number of data that can be written to the RAM.

Number of data per initialization bus frame: This defines the size of each initialization bus frame. The Init Bus Ram Interface block uses data id bits as part of the RAM write address (LSBs of the write address) and will pad with the necessary bits from Initialization Bus address to build the RAM write address.

Inputs

Init Bus: The decoded data stream from the Init decoder's output signal should be connected to this port.

Outputs

Addr_wr: Address signal to connect to the Xilinx Ram block on one of the address port. The signal format is a UFIX signal with the width specified in the "RAM Address width" parameter.

This signal is the result of the concatenation of a part of the Initialization Bus' data id and address (data id composing the LSBs of the RAM address). This means the first data of the first frame will be written first, then the second data of the first frame etc... up to the end of the frame. Then for the next frame the address property of the frame needs to be incremented to write in a new space all the data from the frame. This needs to be repeated as long as necessary to send the required amount of data.

The total number of data written will be (number of frame)*(number of data per frame) which should be equal to 2^(RAM Address width).

Data: Data signal to connect to the Xilinx Ram block on one of the data (din) port. The signal format is a UFIX signal with the width specified in the "RAM Data width" parameter.

We: Write enable signal to connect to the Xilinx Ram block on one of the write enable (we) port.This signal is a boolean.

Reset: Reset signal inherited from the init bus. This signal is a boolean.

Characteristics and limitations

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