The model is composed of two main subsystems:

• SC_eHS: Subsystem executed by the host computer during the simulation to monitor and control the simulation.
• SM_eHS: Subsystem executed by the target simulator, in real-time, on the system CPU that communicates with the FPGA board and the physical system I/Os.

SC_eHS

Double-click the SC_eHS subsystem to open the SC_eHS details window.

SM_eHS

Double-click the SM_eHS to open the SM_eHS details window. This window provides a detailed diagram of the Master subsystem.

eHSx32 for OP4200 Block

The eHSx32 for OP4200 block communicates with the FPGA board to initialize the eHS core. During real-time operation, it provides eHS inputs (the circuit’s Sources and Gates control signals) and reads the eHS outputs (the circuit’s current and voltage measurements) at the RT-LAB model rate.

The user must provide a circuit file (SimPowerSystems Simulink model, PSIM file, or PLECS Simulink model) to declare the circuit that will be simulated inside the eHS core. To declare a specific circuit file, double-click on the eHSx32 for OP4200 block to open the graphical user interface. In the Circuit tab, a circuit file can be selected and parsed. In this example, the circuit file is a SimPowerSystems Simulink model entitled Boost_and_2LvInverter_SPS.mdl.

Navigating to the Gates tab will display and list the switches that are present in the declared circuit file. The Gates tab allows the user to configure the Switch Source Type & Channel for each switch (either from a Digital In channel or from the CPU), the polarity of each switch (High or Low), and the Switch Conductance (Gs) value of each switch.

Navigating to the Inputs tab will display and list the circuit inputs that are present in the declared circuit file.

The Inputs tab allows the user to configure the different Current and Voltage Sources used in the circuit model as well as the parameters (used to configure the value of the Constant) of each input. By selecting CPU, the block regeneration will expose this input as an input port to the block.

Navigating to the Outputs tab will display and list the circuit outputs that are present in the declared circuit file.

The Outputs tab allows the user to view the measurement points configured within the circuit model.

Circuit File

The circuit file models a boost and a two-level inverter. The eHS solver will extract the components netlist from this file and calculate the system equations before running them on the FPGA board.