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V2.17 Kintex-7 410T - eHS x128 - PMSM - IMwithSAT - IO Config2

Owned by Fabien Ducat
Mar 14, 2024

OPAL-RT TECHNOLOGIES
1751 Richardson suite 1060, Montréal QC Canada H3K 1G6
www.opal-rt.com

© 2023 OPAL-RT TECHNOLOGIES All rights reserved

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SPS WORKFLOW SCHEMATIC EDITOR WORKFLOWSCHEMATIC EDITOR WORKFLOW WITH SFUNCTION

Introduction

This firmware includes:

  • One eHS x128 Gen4 Solver
  • One Dual Permanent Magnet Synchronous Machines (PMSM-VDQ) model
  • One Quad Generic Machines (GM) model
  • One Analog Output Mapping and Rescaling (AOMR) module
  • One Analog Input Differential Rescaling (AIR) module
  • One Thermal Losses (TL) module
  • One Saturable Transformer (satXFO) module


LoadIn/DataIn/DataOut mapping


LoadIn

DataIn

DataOut

1

Config eHS

Inputs eHS

eHS Averaged

2

Scenario / Rst eHS = Status

TSDO 1 - eHS 0 to 7

eHS DownSample

3


TSDO 2 - eHS 8 to 15

Digital In 1A - 0 to 7

4

PWM 1A -  0 to 7

TSDO 3 - eHS 16 to 23

Digital In 1A - 8 to 15

5

PWM 1A -  8 to 15

TSDO 4 - eHS 24 to 31

Digital In 1A - 16 to 23

6

PWM 1A -  16 to 23

TSDO 5 - eHS 32 to 39

Digital In 1A - 24 to 31

7

PWM 1A -  24 to 31

TSDO 6 - eHS 40 to 47

Analog In 2A - 0 to 7

8


TSDO 7 - eHS 48 to 55

Analog In 2A - 8 to 15

9


TSDO 8 - eHS 56 to 63

PMSM VDQ 1/2

10


TSDO 9 - eHS 64 to 71

Encoder Input on RS422

11


Digital Out 1A - SDO 0 to 7

Quad Generic Machine with SAT

12

Config AOMR

Digital Out 1A - SDO 8 to 15

Encoder Input on Digital In 1A

13

eHS PWM 1 - eHS 0 to 7

Digital Out 1A - SDO 16 to 23

Thermal Losses

14

eHS PWM 2 - eHS 8 to 15

Digital Out 1A - SDO 24 to 31

RMS and Power calculation

15

eHS PWM 3 - eHS 16 to 23



16

eHS PWM 4 - eHS 24 to 31



17

Config eHS AIR



18

Config PMSM VDQ1/2



19

Config Encoder Input on RS422

AOMR/ Analog Out 1B -  0 to 7


20

Config Quad Generic Machine with SAT

Analog Out 1B -  8 to 15


21

Config Encoder Input on Digital In 1A

Analog Out 2B -  0 to 7


22

Config Thermal Losses

Analog Out 2B -  8 to 15


23

Config Encoder Output on RS422

eHS PWM 1 -  0 to 7


24

SFP

eHS PWM 2 -  8 to 15


25

Lookup Table Config

eHS PWM 3 -  16 to 23


26

RMS and Power calculation

eHS PWM 4 -  24 to 31


27


eHS SWG


28


PMSM VDQ 1/2


29
Quad Generic Machine with SAT

30


Thermal Losses


31
Encoder Output on RS422
32
LEDs
33
TSDO 10 - eHS 72 to 79
34
TSDO 11 - eHS 80 to 87
35
TSDO 12 - eHS 88 to 95
36
TSDO 13 - eHS 96 to 103
37
TSDO 14 - eHS 104 to 111
38
TSDO 15 - eHS 112 to 119
39
TSDO 16 - eHS 120 to 127
40
TSDO 17 - eHS 128 to 135
41
TSDO 18 - eHS 136 to 143
42
SFP
43
Lookup Table Config

System Overview


Extensive I/O compatibility (Polymorphism)

Listed cards are compatible at the same location

Digital In/Out Mezzanine

Compatible Mezzanine Modules

OP5369


Analog Out Mezzanine

Compatible Mezzanine Modules

OP5330-3 16 Aout

OP5330-1 16 Aout


Analog In Mezzanine

Compatible Mezzanine Modules

OP5340-1 16 Ain

OP5340-2 16 Ain 

Expansion Mezzanine

Compatible Mezzanine Modules

OP5969-1 DIN/DOUT RS422 5V

OP5969-2 DIN/DOUT FIBER OPTIC


eHS solver

SPS WORKFLOW SPECIFIC

Connectivity

SPS WORKFLOW SPECIFIC

Source TypeSource IndexSource NameDetails
Input

0CPU Input
1eHS Analog InSlot 2A - Ch00-15
2PMSM VDQ 1/2PMSM1 Ia/PMSM1 Ib
PMSM2 Ia/PMSM2 Ib
3Sine Wave Generator
4Quad Generic Machine

IM1 Stator Ia/IM1 Stator Ib/IM1 Rotor Ia/IM1 Rotor Ib

IM2 Stator Ia/IM2 Stator Ib/IM2 Rotor Ia/IM2 Rotor Ib
IM3 Stator Ia/IM3 Stator Ib/IM3 Rotor Ia/IM3 Rotor Ib
IM4 Stator Ia/IM4 Stator Ib/IM4 Rotor Ia/IM4 Rotor Ib
5Data stream from SFP #00
Gate0CPU Gating Signal
1PWM
2Digital InputSlot 1A - Ch00-31

SPS WORKFLOW SPECIFIC

To contextualize the Input and Gate Configuration table with this firmware configuration, the eHS firmware config tab must be configured with the following custom input source enumeration:

{'CPU Model',0,64;'Sine Wave Generator',3,32;'PMSM',2,4;'GM',4,16}

And this custom gate sources enumeration:

{'CPU Model',0,72;'Digital Inputs',2,32;'PWM',1,32}

Permanent Magnet Synchronous Machine models (PMSM VDQ)

A total of two PMSM motors are available and configured using the Permanent Magent Synchronous Machine. The machine type could be Constant DQ, Variable DQ or BLDC. 


Schematic Editor Workflow - PMSM (VDQ - BLDC) block

SPS Workflow - PMSM (VDQ - BLDC) block

Communication port configuration for the Dual PMSM (VDQ) block

      

Dual PMSM Motors VDQ

Machine Label

PMSM 1

PMSM 2

Data In Port Number

28

Load In Port Number

18

Data Out Port Number

9

Connectivity (Input)

The signals received could be used as external carrier for machine resolver module. 
Analog In - Slot 2A - Ch00-01

Encoder Output

Encoder outputs are sent to 
Digital Out - Slot 3B - RS422

Hardware Pin assignment

Quad Generic Machine model (GM)

A total of four Induction Machines (IM) are available and configured using Generic Machine block in the eFPGAsim library.

Schematic Editor Workflow - Generic Machine block

SPS Workflow - Generic Machine block

Communication port configuration for the Quad Generic Machine (GM) block

      

Quad Generic Machine

Machine Label

IMwithSAT 1

IMwithSAT 2

IMwithSAT 3IMwithSAT 4

Data In Port Number

29

Load In Port Number

20

Data Out Port Number

11

Connectivity (Input)

The signals received could be used as external carrier for machine resolver module. 
Analog In - Slot 2A - Ch00-01

Encoder Output

Encoder outputs are sent to 
Digital Out - Slot 2B


Encoder 1Encoder 2
ACh00Ch04
BCh01Ch05
ZCh02Ch06

Hardware Pin assignment

Thermal Losses module (TL)

SPS WORKFLOW SPECIFIC

There is one Thermal Losses tab in the eHS CPU block allowing to configure all four thermal models.

SPS Workflow - Thermal Losses (TL) block

Communication port configuration for the Thermal Losses (TL) block


Thermal Losses
Data In Port Number30
Load In Port Number22
Data Out Port Number13

Power calculation module

SPS WORKFLOW SPECIFIC SCHEMATIC EDITOR WORKFLOW WITH SFUNCTION

RMS and power calculation for all circuit measurements is configured using the “Power Measurement Controller” block in the CPU model.

For more documentation on the block see : https://opal-rt.atlassian.net/wiki/spaces/PFPET/pages/65835684/CPU+Power+Measurement+Configuration+-+efs+Monitoring+cpuPowerBlock

Communication port configuration for the Power calculation block


RMS
Load In Port Number26
Data Out Port Number14

Analog Output Mapping and Rescaling module (AOMR)

AUTOMATIC AND NOT VISIBLE IN SCHEMATIC EDITOR WORKFLOW

There is one AOMR block allowing to configure all 32 analog outputs.

AOMR Master Subsystem (SM) block

Communication port configuration for the Analog Output Mapping and Rescaling (AOMR) block


AOMR - Slot 2B

VersionV2
Data In Port Number19
Load In Port Number12

Analog Input Differential Rescaling module (AIR)

AUTOMATIC AND NOT VISIBLE IN SCHEMATIC EDITOR WORKFLOW

AIR block configures analog inputs for eHS.

AIR block

Communication port configuration for the Analog Input Differential Rescaling (AIR) block


AIR - Slot 2A

ChannelsCh00-15
Load In Port Number17

AOMR Output

Lane IndexSignal SourceDetails
0eHS OutputseHS Y01-128
1PMSM VDQ 1/2 AnalogOutDual PMSM VDQ Model
2Quad Generic Machine AnalogOutQuad Generic Machine Model
3Data Stream from SFP #01


SFP Mapping and Communication Block

A total of 32 inputs and 32 outputs are available and configured using the SFP mapping and communication block.

Schematic Editor Workflow - SFP Mapping and Communication block


Communication port configuration for the SFP mapping and communication block


SFP - Channel 0

Data In Port Number42
Load In Port Number24

Analog In module (AI)

AI block reads signals from analog input channels on the simulator. 

SPS Workflow - AI block



Schematic Editor Workflow - OPAL-Board/AI

RT-LAB

HYPERSIM


Communication port configuration for the Analog Input (AI) block


Slot 2A 

ChannelsCh00-07Ch08-15
Data Out Port Number78

Connector Pin Assignment

Please refer to your hardware documentation

Hardware Pin assignment


Analog Out module (AO)

AO block configures analog output channels on the simulator. 

SPS Workflow - AO block


Schematic Editor Workflow - OPAL-Board/AO

RT-LAB

HYPERSIM


Communication port configuration for the Analog Output (AO) block


Slot 1B

Slot 2B

ChannelsCh00-07Ch08-15Ch00-07Ch08-15
Data In Port Number19202122

Connector Pin Assignment

Please refer to your hardware documentation

Hardware Pin assignment


Digital In module (DI)

DI block reads signals from digital input channels on the simulator. It could be static, TSDI or PWMIn.

SPS Workflow - DI block

Schematic Editor Workflow - OPAL-Board/DI

RT-LAB

HYPERSIM


Communication port configuration for the Digital Input (DI) block


Slot 1A 

ChannelsCh00-07Ch08-15Ch16-23Ch24-31
Data Out Port Number3456

Connector Pin Assignment

Please refer to your hardware documentation

Hardware Pin assignment


Digital Out module (DO)

DO block configures digital output channels on the simulator. It could be static, TSDO or PWMOut.

SPS Workflow - DO block

Schematic Editor Workflow - OPAL-Board/DO

RT-LAB

HYPERSIM


Communication port configuration for the Digital Output (DO) block


Slot 1A 

ChannelsCh00-07Ch08-15Ch16-23Ch24-31
Data In Port Number11121314
Load In Port Number4567

Connector Pin Assignment

Please refer to your hardware documentation

Hardware Pin assignment


Encoder Input module (ENC IN)

Encoder Input block reads signals from specific input channels on the simulator.

SPS Workflow - Encoder Input block

Schematic Editor Workflow - OPAL-Board/ENC In

RT-LAB

HYPERSIM


Communication port configuration for the Encoder Intput (ENC IN) block


Slot 3A - RS422 

Nb of Encoder Signals2
Load In Port Number19
Data Out Port Number11

Connector Pin Assignment

Please refer to your hardware documentation

Hardware Pin assignment


Encoder Output module (ENC OUT)

Encoder Output block configures specific output channels on the simulator.

SPS Workflow - Encoder Output block

Schematic Editor Workflow - OPAL-Board/ENC Out

RT-LAB

HYPERSIM


Communication port configuration for the Encoder Output (ENC OUT) block


Slot 3B - RS422 

Nb of Encoder Signals2
Data In Port Number31
Load In Port Number23

Connector Pin Assignment

Please refer to your hardware documentation

Hardware Pin assignment

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