v2.18 Release Notes

Deprecated

Removed support of x32 libraries following the end of support of x32 OS on Targets.

Support new component CPU-FPGA Stubline.
Added Custom Model XSG Block. Allows users to create custom XSG features and seamlessly connect to eHS.
Modified XSG Digital Input Mapping to specify input IO Slot. How to create FPGA-based Custom Model compatible with Schematic Editor workflow
Improve the S-Function workflow, to load the configuration file before the start of simulation in RT-LAB.
Support Matlab 2024a.
Support OP4810 Versal chassis (Example in the Versal Dual Active Bridge example model).

Fix Analog Aout Clipping for all OP45XX bitstreams.
Fix FDLine minimum time-step with eHS Gen5.
Fix encoder Number of Pulse Per Rotation saturating at 8191 instead of 16383.
Fix SFP outputs that where not working anymore with eHS.
Removed the Analog In Slot 2C information in the Versal IOConf since we can only have 16 AnalogIn channels connected with eHS.
Fix SFP unusual large latency.
Fix FPGA Scope not to prevent from Loading an eHS Circuit.
Fix Encoder signal not getting outputed for bi-directional Digital IO on all bitstreams.
Fixed reversed digital gating signals to eHS.
Fix incorrect behavior of half-bridge switch topology in eHS Gen5.
Increase maximum value for Variable RL and RC in the Schematic Editor.
Fix Copy Paste of NPC component in Schematic Editor workflow
Fix Schematic Editor Single Phase 2/3 windings mutual inductance Resistances to support null values.