Introduction

This document describes how to create a FPGA-based custom model that will connect to other ioconf compatible features and be included in automatic firmware description file generation.

Requirements

• eFPGASIM 2.18 and higher

• RT-XSG 3.5.0 and higher

FPGA-Based custom model

With the introduction of automatic ioconf firmware description file generation in eFPGASIM 2.15 and RT-XSG 3.4.0 it is now possible to automatically create the ioconf file of a given firmware model during the bitstream compilation process. As of eFPGASIM 2.15 and RT-XSG 3.4.0, only official feature blocks were supported but a custom model toolbox block as now been added to eFPGASIM.

When designing FPGA-based models with eFPGASIM and RT-XSG, it is common to want to add custom features to connect to other eFPGASIM features, mainly eHS. In order for that custom model to be usable in Schematic Editor, it needs to:

• Add a custom block instance to the list of firmware blocks

• Add External ports to the port definition of the ioconf

• Add a connection to an eHS FLWS input

• Add a connection to an eHS output lane

All this is now possible with the addition of the “Custom Model” block in the “Toolbox Custom Model” library

How to use the Custom Model block

In order to create your own custom model, simply:

1. Drag and drop the Custom Model block from the library into your model.

   Open

   

2. Connect your custom model to an eHS FLWS input, the eHS low latency output and a new Load In.

   Open

   

    

3. Now that the custom model is imported, open the mask. Inside the mask are editable text fields to specify the names of the signals. Leave them as is or edit them. Once the proper signals are set, click the “Open Custom Model Design” button to start editing. If you need any extra inputs or outputs coming from or going to other blocks other blocks then eHS, use the Provide Input/Output Bus checkboxes. These checkboxes respectively add an input and output port to the custom model that can be used to input or output Simulink buses.

    

4. Add your custom FPGA-based logic under the block and connect your inputs and outputs. Notice the path, under the “custom” subsystem is exclusively where modifications to the model should be made. This subsystem is opened via the “Open Custom Model Design” button. The signal needs to respect the FLWS protocol and are expected to be Extended Floats (XFLOAT_8_34).

5. Once your design is complete, the model is ready for bitstream and ioconf generation

6. Generate the ioconf file and your feature should now be visible in the Schematic Editor’s external model inputs and outputs!

Troubleshooting

If you’re experiencing issues, make sure to check the eFPGASIM with RT-XSG Module quick guide.