Documentation Home Page HIL2GO Main Menu
Pour la documentation en FRANÇAIS, utilisez l'outil de traduction de votre navigateur Chrome, Edge ou Safari. Voir un exemple.

HIL2GO-310 - System Power On and Power Off Sequences

Page Content

TARGET COMPUTER RE-BOOT WARNING: Follow the Power On/Off sequence as indicated below. Failure to do so may require rebooting of the Target.

image-20240627-184827.png
Power On and power Off sequences

Power On Sequence

  1. Power on the OP4810-IO

  2. Power on the OP5020XG

If the OP5020XG (which is running RT-LAB on the target) is powered on before the OP4810-IO, RT-LAB won't be able to detect the present of OP4810-IO FPGA Processor and I/O Expansion Units.
When the power on sequence is executed correctly, the 'Get I/O info' tool in RT-LAB will display the FPGA card enumeration in the Console tab.

image-20240916-202111.png
Get I/O info

Power Off Sequence

  1. Power off the OP5020XG

  2. Power off the OP4810-IO

Disconnecting or powering off the OP4810-IO during operation will require a power Off sequence followed by a power on sequence in order to resume reliable operation.

OPAL-RT TECHNOLOGIES, Inc. | 1751, rue Richardson, bureau 1060 | Montréal, Québec Canada H3K 1G6 | opal-rt.com | +1 514-935-2323
Follow OPAL-RT: LinkedIn | Facebook | YouTube | X/Twitter