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HIL2GO-310 - Your System Information and Specifications
This section presents the HIL2GO-310 system bundle and describes its technical specifications.
Section Content
- HIL2GO-310 - System Overview
- HIL2GO-310 - OP5020XG CPU-based Real-time Simulator Hardware Description
- HIL2GO-310 - OP4810-IO FPGA Processor and I/O Expansion Unit Hardware Description
- HIL2GO-310 - Mapping I/O Blocks to Signal Conditioning In RT-LAB
- HIL2GO-310 - OPAL-RT Controller Configuration
- HIL2GO-310 - I/O Bitstream Name and I/O Configuration
- HIL2GO-310 - OP4810-IO I/O Channels Assignment
- HIL2GO-310 - OP4810-IO I/O System
- HIL2GO-310 - I/O Slot 1, Section A, P1 and P2 (CH 00-31) - Digital Inputs or Outputs (OP48H10)
- HIL2GO-310 - I/O Slot 1, Section B, P3 (CH 00-15) - Analog Outputs (OP48H10)
- HIL2GO-310 - I/O Slot 1, Section C, P4 (CH 00-15) - Analog Inputs (OP48H10)
- HIL2GO-310 - I/O Slot 2, Section A, P1 and P2 (CH 00-31) - Digital Inputs or Outputs (OP48H10)
- HIL2GO-310 - I/O Slot 2, Section B, P3 (CH 00-15) - Analog Outputs (OP48H10)
- HIL2GO-310 - I/O Slot 2, Section C, P4 (CH 00-15) - Analog Inputs (OP48H10)
- HIL2GO-310 - I/O Slot 3, Section A and B (CH 00-05) - RS422 Digital Inputs/Outputs (OP5969)
- HIL2GO-310 - MuSE and SFP Channels