Documentation Home Page ◇ HIL2GO Main Menu
Pour la documentation en FRANÇAIS, utilisez l'outil de traduction de votre navigateur Chrome, Edge ou Safari. Voir un exemple.
HIL2GO-100 - OPAL-RT Controller Configuration
To use OPAL-RT I/O modules, an OpCtrl block is required in the RT-LAB model.
This block controls the programming of one OPAL-RT FPGA, its initialization and the selection of the hardware synchronization mode of the card.
It also enables binding of Send/Recv and I/O blocks to that specific card.
The OpCtrl block can be found in the Simulink block library path: RT-LAB I/O > Opal-RT > Common > OpCtrl
In the integration test model (loopback test) provided, the block parameters for the OpCtrl block are already set as follows.
In your model, use this bitstream.
This information is provided for reference, mostly for advanced users. Most users will want to use it “as is.”
OPAL-RT controller parameters | |
Parameter | Value |
Controller Name | 'OP4512 OpCtrl' |
Board ID | 0 |
Primary Bitstream FileName | TE0741_4-EX-0001-3_4_0_814-eHSx128_Gen4_Machines_IOConfig2-3C-16.bin |
Synchronization mode | Master |
Generate External Clock | ☐ (Unchecked) |
Sample Time (s) | 0 |
Board Type | TE0741 |
Synchronization type | Optical fiber (strongly recommended) / Audio |
Disable strict hardware mismatch validation | ☐ (Unchecked) |
I/O signals used in the model will be active ONLY if the model is run in Hardware synchronized mode.
OPAL-RT TECHNOLOGIES, Inc. | 1751, rue Richardson, bureau 1060 | Montréal, Québec Canada H3K 1G6 | opal-rt.com | +1 514-935-2323
Follow OPAL-RT: LinkedIn | Facebook | YouTube | X/Twitter