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RT-XSG 3.x Release Notes

Owned by Sylvain Ménard
Last updated: Feb 23, 2024 by Francis Cossette

Version 3.4.0

New

  • AMD-Xilinx Vivado, ModelComposer, 2022.2 support (FPGA-1351)
  • New SPI slave block allowing different sizes of MISO and MOSI. New design also allows to receive and send messages at different times (FPGATT-1236)
  • New I2C Master and Slave blocks (FPGATT-1240)
  • Added Digital Input card OP5367-6, which is a variation of the OP5367-5 with 10x its impedance, and a different board Id (0xE6) (FPGATT-1326)

Bug Fixes

  • Fixed unresolved links in OP5367 IO Block library (FPGATT-1205)
  • Fixed the bitbasher on the 2nd channel for Sine_in in the Resolver Input Subsection block (FPGATT-1179)

Deprecation

  • Removed support for Vivado 2017.x and MATLAB R2016b and R2017a. New minimal supported versions are therefore Vivado 2018.1 and MATLAB R2017b (FPGA-1368)
  • Removed support for OP4200 (FPGA-1366)

Version 3.3.6

Bug fixes

  • Increase a configuration watchdog timer for accommodating a big uncertainty on the Xilinx internal oscillator for Kintex-7 410T (FPGATT-1170).
  • Clock domain formalization for covering sporadic issues on analog board's EEPROM content loading for Artix-7 (OP5143) FPGA-based simulators  (FPGATT-1210).

Version 3.3.5

Bug fixes

  • Correction on PCIe/DMA data corruption on OP5143/Artix-7 due to a combinatorial synthesized logic inference (FPGATT-1204)

Version 3.3.4

Features

  • Xilinx Vivado, ModelComposer, 2022.1 (FPGA-1288)
  • MathWorks MATLAB R2021b (FPGA-1288)
  • 64 LoadIn and LoadOut ports support, with choice of grayzone for 64 or 32 ports (FPGATT-761)
  • OP5369 -> OP5353 & OP5360-# Asymetric Polymorphism (FPGATT-1031, FPGATT-1026)
  • PWMO Dynamic Phase Control, enlarged frequency range and with disable button added (FPGATT-1036/FPGA-1264/FPGATT-1165)

Bug fixes

  • Frequency and strategy selection stays selected after selecting different FPGA Development Board (FPGATT-1064)
  • MuSE overruns and done flag in remote fixes (FPGATT-1136/FPGATT-1159)

Version 3.3.3

Features

  • Bitstream generation strategies (FPGATT-897)
  • Vivado 2021.1, 2021.2 and Matlab 2021a support (FPGATT-1264)
  • OP5367 (Driver&Application driven) (FPGATT-997, FPGATT-1012, FPGATT-1014)
  • DOV's improvement, simulation states signals are now added by default to the ILA Core (FPGATT-953)
  • EnDAT with RecoveryTimeI as an input feature addition (FPGATT-1017)
  • Removed DataIn protection, refer to DOV instead (FPGATT-867)
  • Synthesized Netlist management improvement (FPGATT-942)
  • OP5360-3 support


Bug fixes

  • EnDAT: fix on number of clock cycles for certain commands and slave issues (FPGATT-1001, FPGATT-1000)
  • FLWS Dummy block support under 100 MHz (FPGATT-1028)
  • OP5369: No default direction reprogramming for 32 ports option (FPGATT-1006)
  • OP5369: Bitstream generation without error for unused declared OP5369 mezzanine (FPGATT-1021)
  • RT-XSG model revision MinorID can be "00" (FPGATT-891)
  • HCIG for RCP AIN (FPGATT-996)


Version 3.3.2

Features

  • XilinxVivado 2020.1 and 2020.2 support
  • MathWorks MATLAB R2020a and R2020b support.
  • OP5330 configurable rate (not only determined by the bitstream anymore)
  • OP5033XG / Industrial PC without IOs support - OP5143 FPGA Board with Artix-7


Bug fixes

  • Limiting search of DCP-files to RT-XSG model folder (no more sub-folders)
  • Improved time of Simulink and Vivado regarding SDI and SDO logic
  • HCIG: Resolver feature when automatically generating .opal file
  • Retro-compatibility and usage of I/O Blocks

Version 3.3.1

Features

  • OP5369 Digital configurable direction and threshold - 32 channels, for OP4510, OP5707 and OP5650
  • Aurora CRC error injection option
  • XilinxVivado 2020.1 BETA support
  • MathWorks Matlab 2020a BETA support

Bug fixes

  •  Known limitation on the OP5369 threshold values programming, on Load state, the values can be not programmed, there are Python scripts that are available for fixing values with OPAL-RT Support assistance (FPGATT-858)
  • Critical timing constraint correction on Aurora/MuSE/PCIe (FPGATT-877)
  • OP5650 - Artix-7 New Gray Zone lightened for having more FPGA resources (without MuSE or Aurora) (FPGATT-848)
  • Remove Vivado "Advanced sub-tool" options, available for advanced users, options managed by an environment variable (FPGATT-847)
  • Copy of an IO Block configuration loss correction (FPGATT-833)
  • MuSE Robustness on SFP cable disconnection and unlock faulty Remote programming (instead of a Central)

Version 3.3.0

RESTRICTED RELEASE

Features

  • Added new FPGA Acquisition module during bitstream generation, enabling acquisition of signals internal to the RT-XSG model at an acquisition rate higher than the CPU-based simulation rate
  • OP8110 (ZX5_AMPLI_4Q) beta support
  • OP5369 beta support

Bug fixes

  • Fixed regional time settings error by specifying the "datestr" function to use the 'local' system's parameters
  • Fixed on reporting error leading to a status=11 on compiling DOV source
  • Fixed 2019b support by not using the same name (FileReader) as a class name and a variable name (FPGATT-624)

Version 3.2.11

RESTRICTED RELEASE

Features

  • None

Bug fixes

  • Xilinx PCIe mismacth with hidden HPE bridge parameter - "TD bit" and ECRC check" option to be enabled in the Xilinx PCIe IP core (FPGATT-569).

Version 3.2.10

Features

  • None

Bug fixes

  • Aurora block had a wrong parameter's value.
  • OP5342 timing for all FPGAs.
  • Compatibility with R2016b.

Version 3.2.9

RESTRICTED RELEASE

Features

  • HCIG: IEC60044-8 support.

Bug fixes

  • Bitstream's generation: constraints application fix (FPGATT-595) and error reporting (FPGATT-592).
  • OP5342 at 2.000 MSPS in OP4200 with CPU at 1 GHz and FPGA at 200 MHz (FPGA-427). It was 1.98 MSPS.
  • DOV: Enabled the resize of the configuration window (FPGATT-369).

Version 3.2.8

Features

  • SPI block support
  • OP5367(driver&application driven BETA), 16 Digital IN with programmable threshold and 16 digital OUT support for OP4510 only
  • OP5334, 16 analog OUT 2 MSPS non-isolated beta support for OP5650, OP5707, OP4510 and OP4200
  • HCIG update with Time Stamp Bridge (TSB) support
  • Vivado 2019.2 with MathWorks Matlab 2019a and 2019b BETA support
  • Obsolescence warning on Vivado 2015.3 and 2015.4 with Matlab 2014b, 2015a and 2015b next RT-XSG revision

Bug fixes

  • OP5143/Artix-7 timing closure improvement

  • MuSE remote crash detection bug fix for all systems

Version 3.2.7

Features

  • Improvement by providing designer help by warning the DataIN/OUT blocks configurations without FIFO use (FPGA-345)
  • Added protection in user interface of DataIn/DataOut blocks to warn the user to use FIFO mode when the blocks are connected to analog I/O blocks (FPGA-345, 346)

Bug fixes

  • OP7000 V2 - Primary FPGA (OP7170_1) - bug fix on Analog OUT outputting 0V when
  • Default Output Value (DOV) is activated and when the OP7000 is in slave mode (OP7000NG-491)
  • OP7000 V2 - Primary FPGA (OP7170_1) - bug fix on synchronization signaling when the OP7000 is connected to a second OPAL-RT unit in slave mode (OP7000NG-484)
  • Correction on OP5332 netlist for OP5#07 only. (FPGATT-318)

Version 3.2.6

  • Added Default Output Value support during Pause and Reset simulation states, set by default to 0V, but is modifiable from the Hardware Configuration panel for each channel.
  • Support for OP7000 V2 Primary FPGA board (OP7170-1) with Kintex-7 FPGA (XC7K410T-2FFG900).
  • New option to disable MuSE support for freeing up FPGA resource for OP4510/325T, OP4510/410T and OP5#07. This option is accessible via the Architecture Type parameter of the Synthesis Manager block.
  • Vivado 2018.3/Matlab 2018a support.
  • Vivado 2019.1/Matlab 2018b support.
  • HCIG update with Resolver support. (FPGATT-203)

Version 3.2.5

  • Increased maximum number of CPU-FPGA DataIn/DataOut communication ports to 64. This modification is available for all platforms but OP4200.
  • Added support for new OP7000 Primary FPGA board (OP7170-1) with Kintex-7 FPGA (XC7K410T- 2FFG900). This support is in BETA mode. (OP7000NG-215)
  • Added support for new OP5367 (LoadIn version) TypeB mezzanine module with 16 DIN with programmable threshold and 16 DOUT. The module is presently supported on OP4510 only (BETA).
  • Added option for endianness control for Generic Aurora communication. (FPGATT-312)
  • Fixed problem when loading EEPROM gain and offset values for OP5332 when running at 200 MHz, which caused undesired negative output glitches on some channels. (FPGATT-318)
  • Fixed issue in I2C sequencer that prevented the proper output of the hardware synchronization pulse on the OP5650 (Artix-7) platform. (FPGATT-334)

Version 3.2.4

RESTRICTED RELEASE

  • Mezzanine list correction by showing at the top the value "empty". (FPGATT-263)
  • RT-XSG multi-rate support correction (decimation different than the user clock period that needs to implement clock enable logic by Vivado). (FPGATT-288)
  • Updated the HCIG for the RT-XSG schematic support of Goto/From and bus selector blocks.
  • MuSE updated with more larger DMA transfer size > 64 KB and improved the synchronization with time out when the remote doesn't respond (i.e. is not a real MuSE remote).
  • Added RT-XSG model examples, particularly for the OP5650.

Version 3.2.3

  • OP5600/OP5143 (Artix 7) with MuSE support (without eHS). (FPGATT-266)
  • Multi-voltage range support corrections.
  • Polymorphism enable register for software / driver control on important information to be redirected to the user.

Version 3.2.2

  • Multi user System Expansion (MuSE) with embedded synchronization logic for OP5#07, OP45#0 and OP4200 (Remote only).
  • MuSE Advanced Synchronization improvements (output synchronization alignment between OPAL-RT simulator units using Central and Remote roles). (IOSFP-555, 557, 572)
  • OP5600/OP5143 (Artix 7) improvements without eHS and without full MuSE support.
  • Signal Integrity constraint support improvements (drive strength and slew rate constraint support with mezzanine's slot and channel resolution).
  • RT-XSG model standardization with new OPAL-RT Polymorphism feature support: grouping IO boards having same functionality, some cross-compatibility look up table on hardware identifiers. (BIS-52, 53)
  • Hardware Configuration and Interconnection Generation improvements (HCIG; .conf/.opal). (FPGATT- 228, 229, 249, FPGA-80, 220)
  • Addition of design examples for learning the optical communication using the OP4510 with its MGT/SFP using the Xilinx Aurora IP CORE. (FPGA-114)

Version 3.2.1

  • Integration of an option to use advanced Xilinx pre-defined parameters for the sub-tools (Tcl commands as "opt_design, map_design, route_design") for increasing the probability of achieving timing closure for tight design/FPGA.
  • Multi User System Expansion (MuSE) with flash update support.
  • Matlab 2018A support for Vivado 2018.2.
  • Vivado 2018.2 support.
  • Vivado 2018.1 support.
  • New FPGA Artix 7 support (xc7a200tfbg676-3) for OP5600/OP5143 product with 8 mezzanines (no MuSE).
  • Script correction for terminating the bitstream generation for the OP4200 with correct name. (FPGATT- 165; FPGATT-178)
  • User clock set to 200 MHz when eHS is detected. (FPGATT-143)
  • Implementation of a power down sequence with 7 Series GTX/GTP design for avoiding PCIe loss with VC707. (https://www.xilinx.com/support/answers/59294.html ; FPGATT-130)
  • Hardware Configuration and Interconnection Generation improvements. (HCIG; .conf/.opal) (FPGATT- 102; FPGATT-183)
  • IO Block configuration and name's logic verification improvements. (FPGATT-106/140)
  • MuSE - Prevent user from generating a remote bitstream containing eHS block. (IOSFP-349)

Version 3.2.0

  • Added support for High-Speed Link (HSL) for 4 first MGT ports for OP5#707 (the limitation of 4 MGTs is the total of Aurora and HSL). HSL is supported for any port for other product. There is no flash update for remote units.
  • Removed support of MMPK7 (OP4500), end of life.
  • Hardware Configuration and Interconnection Generation (HCIG) bug fixes. (RTXSG-49, RTXSG-68, FPGATT-97)
  • Implemented logic to detect eHS block and pops out warning to use 200 MHz if not set. (FPGATT-143)

Version 3.1.10

  • Correction on a bug when changing the hardware configuration. A modification on script opxsgIOBlockUpdate was made to improve the verification of assigned hardware in the model, but the type of the returned value for mezzanine string change whether opening the model or it is already open.

Version 3.1.9

  • OP5607/OP5707 rev.3 support.
  • Reinforced OP5342 reset circuitry for removing metastability that might stall the I2C sequencer.
  • Applying drive specific strengths for OP5352 and OP5360-2 in Virtex7, Kintex7 and Zynq based systems. (PF317500-6 and PF617539-7)
  • Support of the user clock of 200 MHz for the conversion's trigger in the 40 MHz architecture of OP5332. (FPGATT-124)
  • Hardware Configuration and Interconnection Generation (HCIG) bug fixes. (FPGATT-97, FPGATT-127)
  • Xilinx Vivado 2017.3 and 2017.4 support improvements. (FPGA-78, FPGATT-33, FPGATT-139)
  • Support of BiSS-C BETA
  • Support of SSI BETA
  • Message and configuration improvements - Path length's verification: Not applied to Windows 10 systems. (FPGA-139 and FPGATT-33).

Version 3.1.8

  • Added support for Xilinx Vivado 2017.3 and 2017.4 support with Mathworks Matlab R2017b.
  • Added OP5332 (analog OUT @ 2 MSPS) support, added new constraints for OP5342 (Analog IN @ 2 MSPS) and added new clocking domain (64 MHz) for the OP5#07 systems.
  • Updated the I2C Sequencer for reading the new IDs of the 126-0308 rev.4.0. Added register address 0x22018.
  • EnDat 2.2 bug fixes: Modified the EnDat Master Interface "Ready" manager. Now in VHDL, uses the EC_STATE signal from ENDATREDUCED.
  • EnDat 2.2 Master: Added features to prevent the trigger of a EnDat transaction if the previous transaction is not finished or if the bus speed requested "Freq_OEM" is 0 (illegal) or 1 (16 MHz).
  • Updated sample RT-LAB models that guides RT-XSG models (buses BusSelector and BusCreator). (RTXSG-63)
  • RT-XSG block improvement - Auto-assign 'Direction' to 'Both' when an 'ExpansionSignal' card's 'Type' is selected. (FPGATT-47)
  • Message and configuration improvements - Correction on error message display for SynthesisManager when updating block; user clock refreshing function. (FPGATT-78, FPGATT-18)
  • HCIG (Hardware Configuration and Interconnection Generation scripts) bug fixes and updated documentation (auto .conf and .opal generation). (FPGATT-83, FPGA-89, RTXSG-62)
  • Synthesis Manager block and Expansion signal block improvements (clock period refresh and direction assignment). (FPGATT-84, FPGATT-47)
  • OP4200 Zynq @667 MHz (V.1.) and @ 1 GHz (V.2.) Gray Zone selection bug fixes. (FPGATT-81)

Version 3.1.7

  • Added OP5332 support for the OP4510. Updated the Gray Zone with additional clocks and new MMCM port association and updated the interrelated timing constraints. Updated the Version block with additional clocks in the Synthesis Manager block (rtxsg_tools.slx).
  • Made correction in the rtxsg_tools.slx for being visible in Simulink browser RT-XSG/Tools. (FPGATT-59)
  • Enforced support for AOMR. Partial support for eHS. Script corrections in nodeToSubsystem.m.
  • Updated script startPoint_tracebackSignal.m : prints the config file's name generated. Modified get_confBlockInfo.m & create_opal_file.m: major modifications for support of AOMR and eHS.
  • Added support of EnDat 2.2 rotative protocol communication (Master and Slave).
  • OP4200: Added support for Zynq 1 GHz.
  • Encoder Out: A parameter is added for the Z pulse width. It sets the width of the Z pulse slice block under the mask. Encoder Output: New "Synchronization pulse width" added to the documentation. (FPGATT-64)
  • Fixed the error of emcclk when arrive write_bitstream process for OP4500 with Vivado 2016.3. (FPGATT-65)
  • Fixed deadlock on TX_READY signal (TX_READY always stays at zero after a fifo full). (FPGATT-72)
  • Synthesis Manager block: enlarged the FPGA Development board dialog box.
  • Added support Vivado 2017.2 and Matlab 2016B and 2017A.

Version 3.1.6

  • Added support of RS485 TypeB Mezzanine(OP5368) for the OP4510 and OP5707 systems.
  • Vivado 2017.1 and Matlab R2016A support.
  • OP5342 full support for OP4510 and OP4200, restricted support for OP5#07 (specific customer only).
  • Added Hardware Configuration and Interconnections Generation (HCIG) algorithm's scripts and documentation. (GFDB-##)
  • An opVerifyAuroraBlockparams.m is a new script for gathering all Generic Aurora Blocks in a model and proceed to a verification off these parameters: MGT Reset Input use, MGT reference clock (for same MGT Quad), MGT Line rate (or same MGT Quad).(RTXSG-40)
  • Fix the problem of incoherence in the selection of the FPGA between the Synthesis block and the Hardware Configuration block (RTXSG-37)

Version 3.1.5

  • Fixed an issue with the default IPCache and Partition values in the new SynthesisManager block
  • Fixed an issue caused an error when checking the path oh the model
  • Matlab R2015B support. Correction in opxsgGetBitstreamVersion.m. (RTXSG-29)
  • OPAL_RT_VivadoPathCheck for informing through a warning message that some characters in the Vivado temporary path could be harmful.
  • Added a parallelizer and a serializer blocks. (FPGATT-51)
  • OP5342 support for the OP5607 / OP5707 with 1 MSPS limitation: new timing constraints (slot's granularity).
  • Update Synthesis Manager Block: Before setting the interface block parameters, the CarrierName parameter (from the HardwareConfig block) must be verified and updated if necessary.(FPGATT-34)
  • New Synthesis Manager Block: merge Version, Hardware and Synthesis Blocks in the same block (SynthesisManager). This new feature automatically updates older models with the new block.
  • Resynchronisation software: "Update Requests" generation support and overrun's notification (data transfer even if overrun).
  • Update block "Register max fanout": was using efsDisplayCb from eFPGAsim, changed to xsgDisplayCb.
  • Update IO Block GUI: Verify if IO blocks need to be updated/reconfigured after the hardware change in the Hardware Config Block.

Version 3.1.4

  • Error Management - Added function of reporting errors (with file location and line number information (soft/Simulink/libRxx/m/CatchErrorReporter.m).
  • Register-Correction of reading the Alpha ID in the RTXSG version and changing the encoding.
  • MGT/SFP-Added a delay on o_SDA and on o_Z for respecting the I2C specification hold timing of 100 ns for the Si5338 clock generator (clock reference).
  • OP5342-Added support of an analog input mezzanine "OP5342" @ maximum 2 MSPS (but maximum 1 MSPS for OP5#07).
  • MATLAB Function-MCode function to serialize words to the Aurora AXI interface (soft/Simulink/libRxx/m/opxsgGenericAuroraSender.m).
  • Vivado and Windows 7-Apply a workaround to fix problem with 260 characters limitations for PATH in Windows. The problem occurs mostly when Sysgen is generating and synthesizing IP cores.

Version 3.1.3

  • Vivado: Added support of Vivado 2015.4 by taking into account the Xilinx Compilation type "Synthesized_Checkpoint".
  • OP4200: Added support of User LEDs.
  • Vivado: Added support of 2016.3 (added synth_stub option in Tcl script for generating the user model stub) with IP Cache option available for better Synthesis time achievement.
  • OP4510: Fixed issue with Expansion slot IO Block configuration (ExpansionSignal type). (TT#8969)
  • VC707: Updated the Gray Zone by adding dont_touch attribute on configuration clock for generating a bitstream.
  • OP4200 and Vivado 2016.3: Changed a constraint for allowing the generation of a bitstream (SPIx1).
  • Added support of Vivado 2016.4.
  • Updated the Selectable DIO block (specific to the TSDIO functionality) by adding a delay before the Model Synchronization pulse. (TT#8978)
  • Mezzanine OP5342: Added support of the new Analog IN at 2 MSPS for OP4510 and OP5607 with Signal Integrity control (IO's drive strength specific modifications; additional timing constraints).
  • Added new report as hardware configuration file (Product, FPGA, mezzanine names) in the project folder (hw_config.txt).
  • Mezzanine OP5342: Bring correction on safe frequency support of the I2C communication bus under the user clock following (100 or 200 MHz).
  • Selectable DIO: added synchronization on ModelSync for Selectable DO (rtxsg_application_lib.slx).

Version 3.1.2

  • Fixed One step delay in Generic Aurora transmission when one word is transmitted per time step. (TT#8839)
  • Add an option to enable or disable the CRC in the Generic Aurora. (TT#8951)
  • Added support for new IO carrier names of the OP4200 system. (TT#)
  • Added feature to generate the update request internally for OP4500. (TT8937#)
  • Fixed fatal exception again Matlab 2015aSP1. (TT8888#)
  • Modify design to prevent flipping board index problem on OP4510 system. (TT8938#)

Version 3.1.1

  • Fixed Mask Visibility of PWMO block When option "As Block Parameter" is chosen for InitPhase. (TT#8829)
  • Added mask for XSG blackbox resynch_fanout10_ff (register with MAX_FANOUT) attribute.The existing way to instantiate this blackbox manually in the designs has the disadvantage that the value of the MAX_FANOUT attribute is the same across all instances of this blackbox.By using this mask the value of the attribute can be changed with a mask parameter. (TT#8556)
  • Added support for Board Index > 31 for the OP5607 (VC707). (TT#8748)

Version 3.1.0

  • Added a "Selectable DIO" functionnality in RT-XSG. (TT#8791)
  • Added support for Matlab 2015aSP1. (TT#8607)
  • Added support for OP4200 (Zynq 7030) (alpha release). (TT#8741)
  • Added support for OP5363 mezzanine (32 DI High Impedance) for Virtex-7 (OP5700, OP5607), and Kintex-7 (OP4510,OP4520). (TT#8369)
  • Fixed SineCosine block obsolescence in Common/op_cosin block with interpolated-LUT-based sine wave generator. (TT#4472)
  • Fixed Park/Inversed Park transform blocks with updated Common/op_cosin block. (TT#8576, RT3#284360)
  • Fixed an issue preventing the support of space characters in the model path. (TT#8622)
  • Added a mechanism to detect a model crash in Hypersim, so that a protection logic can be implemented for the outputs of the simulator. (TT#8739)
  • Added protection to prevent endless error reporting when performing an update diagram (Ctrl-D) on a model when the Version block name is not exactly 'Version'. (TT#8757)
  • Replaced the feature "open timing analyzer" by a timing text-file report. (TT#8623)
  • Fixed an issue causing timing violation errors when generating bitstreams for OP4500. (TT#8783)
  • Fixed an issue with chassis ID value changing from 0 to 31 after bitstream is programmed on systems with Virtex7 FPGA. (TT#8793)

Version 3.0.0

  • Fixed filtering of input signals for TSDI and PWMI operating at 200MHz. (TT#8573)
  • Added an option in the Version block to force the maximum fanout value for the ModelSync and nRst signals. (TT#8556)
  • Fixed Generic Aurora Communication block to prevent Matlab crash at model opening. (TT#8505)
  • Improved PCIe timing management for Kintex7 FPGA (MMPK7 and TE0741) by relaxing maxskew parameter. (TT#8503)

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