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RT-XSG 3.x Evolution

The table below summarizes the evolution of the RT-XSG 3.x toolbox.

Detailed release notes can be found in RT-XSG 3.x Release Notes.

Version/EventsNew Matlab or Vivado SupportNew Product Support 2014AAll Xilinx Series7’ FPGA based products (OP4510, OP4520, OP5607, OP5707, OP7200) 2014B 2015.3 2015A
OP4200* 2016.3 2016.4 2015B 2017.1
Matlab 2016A 2017.2
Matlab 2016B,
2017A 2017.3,
Matlab 2017B
  • OP5#07 v.3. prototype
  • HCIG v1
  • OP5#07 v.3.
  • BiSS-C (BETA)
  • SSI (BETA)

MuSE (Xilinx Aurora second application)
Vivado 2018.1,
Matlab 2018A
  • OP5143 BETA

MuSE (functionality) : OP5143
  • MuSE (functionality): OP5600/OP5143, OP5650
  • Multi-voltage ranges analog output bug fix
  • Polymorphism enable support

  • Mezzanine list - "empty" on top
  • Multi-rate support correction
  • HCIG support of Goto/From and bus selector blocks
  • MuSE
  • larger DMA transfer size
  • enumeration improvement
  • Addition of model examples (OP5650)
  • Communication through DataIN/DataOUT blocks with 64 ports support (except for OP4200)
  • OP7000v2 BETA support (Primary FPGA board)
  • OP5367 (LoadIn) 16 x DIN with programmable threshold and 16 x DOUT mezzanine for OP4510 only (BETA)
  • Endianness options addition for Generic Aurora communication
  • OP5332 with 200 MHz bug fix for loading EEPROM gain and offset values
  • OP5650 - Fixed synchronization pulse (Artix-7)
3.2.6Vivado 2018.3,
Vivado 2019.1
Matlab 2018b
  • Default Output Values (DOV) support
  • OP7000 V2 Primary FPGA board support (Kintex-7 XC7K410T-2FFG900)
  • New Architecture "No MuSE" for OP4510/325T,410T and OP5#07
  • HCIG update with Resolver support
  • Improvement by providing designer help by warning the DataIN/OUT blocks configurations without FIFO use (FPGA-345)
  • Added protection in user interface of DataIn/DataOut blocks to warn the user to use FIFO mode when the blocks are connected to analog I/O blocks (FPGA-345, 346)

Vivado 2019.2

Matlab 2019b

  • SPI block support
  • OP5367(LoadIN), 16 Digital IN with programmable threshold and 16 digital OUT support for OP4510 only
  • OP5334, 16 analog OUT 2 MSPS non-isolated beta support for OP5650, OP5707, OP4510 and OP4200
  • HCIG update with Time Stamp Bridge (TSB) support
  • Vivado 2019.2 with MathWorks Matlab 2019a and 2019b BETA support
  • Obsolescence warning on Vivado 2015.3 and 2015.4 with Matlab 2014b, 2015a and 2015b next RT-XSG revision



  • HCIG: IEC60044-8 support.
  • Bitstream's generation: constraints application fix (FPGATT-595) and error reporting (FPGATT-592).
  • OP5342 at 2.000 MSPS in OP4200 with CPU at 1 GHz and FPGA at 200 MHz (FPGA-427). It was 1.98 MSPS.
  • DOV: Enabled the resize of the configuration window (FPGATT-369).
  • Aurora block had a wrong parameter's value.
  • OP5342 timing for all FPGAs.
  • Compatibility with R2016b.



  • Added new FPGA Acquisition module during bitstream generation, enabling acquisition of signals internal to the RT-XSG model at an acquisition rate higher than the CPU-based simulation rate.
  • OP8110 (ZX5_AMPLI_4Q) beta support.
  • OP5369 beta support.
  • Fixed regional time settings error by specifying the "datestr" function to use the 'local' system's parameters (FPGATT-638).
  • Fixed on reporting error leading to a status=11 on compiling DOV source (FPGATT-638).
  • Fixed 2019b support by not using the same name (FileReader) as a class name and a variable name (FPGATT-624).


  • OP5369 Digital configurable direction and threshold - 32 channels, for OP4510, OP5707 and OP5650.
  • Aurora CRC error injection option.
  • XilinxVivado 2020.1 BETA support.
  • MathWorks Matlab 2020a BETA support.

Bug fixes

  • Known limitation on the OP5369 threshold values programming, on Load state, the values can be not programmed, there are Python scripts that are available for fixing values with OPAL-RT Support assistance (FPGATT-858).
  • OP5650 - Artix-7 New Gray Zone lightened for having more FPGA resources (without MuSE neither Aurora) (FPGATT-848).
  • Remove Vivado "Advanced sub-tool" options, available for advanced users, options managed by an environment variable (FPGATT-847).
  • Copy of an IO Block configuration loss correction (FPGATT-833).
  • MuSE Robustness on SFP cable disconnection and unlock faulty Remote programming (instead of a Central).

Vivado 2020.1, 2020.2

Matlab 2020a, 2020b

  • Xilinx Vivado 2020.1 and 2020.2 support
  • MathWorks MATLAB R2020a and R2020b support
  • OP5330 configurable rate (not only determined by the bitstream anymore)
  • OP5033XG / Industrial PC without IOs support - OP5143 FPGA Board with Artix-7
  • Limiting search of DCP-files to RT-XSG model folder (no more sub-folders)
  • Improved time of Simulink and Vivado regarding SDI and SDO logic
  • HCIG: Resolver feature when automatically generating .opal file
  • Retro-compatibility and usage of I/O Blocks

Vivado 2021.1, 2021.2

Matlab 2021a


  • Bitstream generation strategies (FPGATT-897)
  • Vivado 2021.1, 2021.2 and Matlab 2021a support (FPGATT-1264)
  • OP5367 (Driver&Application driven) (FPGATT-997, FPGATT-1012, FPGATT-1014)

  • DOV's improvement, simulation states signals are now added by default to the ILA Core (FPGATT-953)
  • EnDAT with RecoveryTimeI as an input feature addition (FPGATT-1017)
  • Removed DataIn protection, refer to DOV instead (FPGATT-867)
  • Synthesized Netlist management improvement (FPGATT-942)
  • OP5360-3 support

Bug fixes

  • EnDAT: fix on number of clock cycles for certain commands and slave issues (FPGATT-1001,FPGATT-1000)
  • FLWS Dummy block support under 100 MHz (FPGATT-1028)
  • OP5369: No default direction reprogramming for 32 ports option (FPGATT-1006)
  • OP5369: Bitstream generation without error for unused declared OP5369 mezzanine (FPGATT-1021)
  • RT-XSG model revision MinorID can be "00" (FPGATT-891)
  • HCIG for RCP AIN (FPGATT-996)

Xilinx Vivado ModelComposer 2022.1

MathWorks Matlab 2021b


  • Xilinx Vivado, ModelComposer, 2022.1 (FPGA-1288)
  • MathWorks MATLAB R2021b (FPGA-1288)
  • 64 LoadIn and LoadOut ports support, with choice of grayzone for 64 or 32 ports (FPGATT-761)
  • OP5369 -> OP5353 & OP5360-# Asymetric Polymorphism (FPGATT-1031, FPGATT-1026)
  • PWMO Dynamic Phase Control, enlarged frequency range and with disable button added (FPGATT-1036/FPGA-1264/FPGATT-1165)

Bug fixes

  • Frequency and strategy selection stays selected after selecting different FPGA Development Board (FPGATT-1064)
  • MuSE overruns and done flag in remote fixes (FPGATT-1136/FPGATT-1159)

Bug fixes

  • Correction on PCIe/DMA data corruption on OP5143/Artix-7 due to a combinatorial synthesized logic inference (FPGATT-1204)


Bug fixes

  • Increase a configuration watchdog timer for accommodating a big uncertainty on the Xilinx internal oscillator for Kintex-7 410T (FPGATT-1170).
  • Clock domain formalization for covering sporadic issues on analog board's EEPROM content loading for Artix-7 (OP5143) FPGA-based simulators  (FPGATT-1210).

*Started with but full support in

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