Block

Mask

Description

This controller block accesses a user-selectable Xilinx ML506 board. The ML506 holds a Virtex 5 FPGA and several I/O lines. Its integration in Opal-RT RT-LAB and RT-XSG products make it possible to connect it to Opal-RT I/O devices and to take advantage of the reprogramming capabilities of the board while designing high performances real-time applications.

The OpCtrl ML506-XSG block provides a standard interface for writing data to and receiving data from, the reconfigurable card. Since the OpCtrl ML506-XSG block has no knowledge of the specific bitstream programmed into the flash memory of the card, it is the responsibility of the user to ensure that data are written to the inports (or read from the outports) of the block in the order required by the bitstream programmed into the board.

See the Characteristics and Limitations section below for indications on card programming and for information regarding model synchronization.

Parameters

Controller Name	Typically, the controller name uniquely specified in an OpCtrl block's parameter enables the binding between a specific controller and generic functionality blocks.
Board ID	This parameter refers to the Board Index of the ML506 board, to be used for SignalWire communications. It is determined by the settings of the first two switches of the SW8 DIP Switch. Please refer to the ML506 documentation for more information.

SW8 Dip Switch Settings

Board ID (decimal/Hex)	Switch 1	Switch 2
15 / 0xF	ON	ON
14 / 0xE	ON	OFF
13 / 0xD	OFF	ON
12 / 0xC	OFF	OFF

The setting of this parameter must follow some synchronization rules as listed below: When several Opal-RT boards (OP5110, SignalWire, ML506) are used in the model, an OpConfigSync block must be placed in the model in order to specify the synchronization source (i.e the "Master" of the synchronization). If an OpConfigSync block is used and does not specify ML506 as the synchronization source with the same board index as this OpCtrl ML506XSG block, the sample time of the OpCtrl ML506XSG block must be an integer multiple of the synchronization source sample time specified in the OpConfigSync block. If an OpConfigSync block is used and specifies the ML506 as the synchronization source and the board index value of the OpCtrlML506XSG block, its sample time must be the fastest rate in the model.
Number of Inports	Enter the desired number of inports for this block. It should be an integer different from 0, between 1 and 16.
Number of Outports	Enter the desired number of outports for this block. It should be an integer different from 0, between 1 and 16.
Bitstream FileName	This is the name of the bit stream expected to be programmed on the ML506 before the model is loaded. The programming of the ML506 is performed by RT-LAB during the load stage. The bitstream must be available in the model directory. The bitstream must have been produced with RT-XSG.
Show Advanced Diagnostics output	When this option is checked,a status output is added to the block. See the Outputs section for details on the status values.
Return External Carriers ID codes	When this option is checked, an additional output is added to the block in order to return the IDcodes of the hardware connected to the ML506 via its backplane connector. See the Outputs section for more details.
Return Mezzanine ID codes	When this option is checked, an additional output is added to the block in order to return the ID codes of the mezzanine modules installed in slot A and B of the ML506. See the Outputs section for more details.
Sample Time (s)	This parameter allows the user to specify the sample time for this block, in seconds. The default value is 0, which specifies a continuous sample time (note that the sample time is obtained from the separated subsystem).

Inputs

The number of inports is controlled by the mask parameter 'Number of Inports'. The type of inports is unsigned 32-bit. The width of each inport can be up to 253 values.

At each calculation step, these input values are written to the data input registers of the board.

Outputs

The number of outports is controlled by the mask parameter 'Number of Outports'. Each outport is a vector of unsigned 32-bit values. The width of each output is defined by the surrounding model but must remain consistent with the capabilities of the bitstream programmed into the reconfigurable board.

At each calculation step, the data output registers of the board are copied to the outputs of the block.

Three additional outports are available. These outports return double values.

The Error outport returns the following error codes:

Value	Description
0	No error.
-1	Card not detected
-2	A mismatch between the amount of output data received from the board and the width of the output ports.
-4	Synchronization timeout error. This error occurs when the ML506-XSG is programmed in slave mode and no RTSI pulse is provided, for example, if the RTSI cable is unplugged.
-10	This error code can be added to the above codes. It indicates a mismatch between the type of hardware selected in BP_A_IO and BP_B_IO blocks in the FPGA model and the actual hardware connected to the ML506 backplane connector.
-100	This error code can be added to the above codes. It indicates that at least one of the mezzanine slots of the ML506 is left empty.
If the Parameter 'Show Advanced Diagnostics output' is checked	a Status outport is added to the block. This outport is used to debug communication problems with the ML506 board and especially to detect mismatches between the data received from the board and the data expected to be received. The width of this outport is equal to the number of data outports specified by the 'Number of Outports'parameter. The elements of the vector contain the number of data values received from the board for each output port.
If the Parameter 'Return External Carriers ID codes' is checked	the IDs outport is added to the block. This outport is used to return identification information regarding the hardware connected to the ML506 board via its backplane connector. Each type of hardware that can be connected to the backplane connector of the ML506 and selected in the BP_A_IOand BP_B_IO of the FPGA model holds a different ID code. Values are in the range 0 to 63 ('0' to '3F' in hexadecimal). The actual hexadecimal value assigned to each hardware can be found by looking at the BoardID block under the mask of the BP_A_IO and BP_B_IO blocks of the FPGA model. Note that the OP5120 carrier does not have an ID code and returns the value 63. This is also the value returned when the adaptor card connected at the back of the ML506 is not an OP5929 or when the BoardID cable of the OP5929 adaptors (JP9) is not plugged. Bitstreamsproduced with older RT-LAB versions do not support the ID codes feature, and the IDs outport returns -1 when such a bitstream is programmed in the ML506.
If the Parameter 'Return Mezzanine ID codes' is checked	the MezzIDs outport is added to the block. This outport is used to return identification information regarding the mezzanine modules installed in slot A and B of the ML506. Values are in the range 0 to 63 ('0' to '3F' in hexadecimal). The ML506 supports two type of mezzanine modules: OP5330 (D/A) and OP5340 (A/D). The OP5340 has MezzID=1, the OP5330 family consists in OP5330-1 (MezzID=0), OP5330-2 (MezzID=2) and OP5330-3 (MezzID=3). If a slot of the ML506 was left empty, the MezzId value returned for this location is 63 ('3F'). Bitstreams produced with older RT-LAB versions do not support the ID codes feature, and the MezzIDs outport returns -1 when such a bitstream is programmed in the ML506. Note that the Error output reports an error only if a slot is left empty.

Characteristics and Limitations

Board Programming

The OpCtrl ML506-XSG block only supports the ML506 boards. The bitstreams for these boards are generated using Xilinx System Generator toolbox for Matlab/Simulink and a blockset of dedicated Opal-RT I/O blocks. These features are integrated in the Opal-RT RT-XSG product (version 1.2 or higher).

Once the bistream is generated, it must be placed in the model directory of each model that uses the OpCtrl ML506-XSG block, and the bistream name must be specified in the Bitstream Filename parameter of the block. Programming of the bitstream into the Flash memory of the board is then performed automatically during the load of the model using the flash_update application.

Note: ML506-XSG bitstreams have the following filename format :
S17-0028-ML506PCIE-<Device_ID>-<Major_ID>-<Minor_ID>-<Revision>.bin

Synchronization

The ML506board can be used in Hardware synchronized mode, both in master and slave mode. In both modes, the ML506 is programmed with the calculation step of the model and its inputs and outputs are updated at each calculation step. In master mode, the ML506 is the board that synchronizes the model, i.e. the synchronization signal of the ML506 determines the beginning of each calculation step. In slave mode, the ML506 accepts a synchronization signal from another I/O board and it synchronizes the update of the inputs and outputs with this external signal. For cabling issues regarding the external synchronization signal, please refer to the documentation coming with your system or contact support@opal-rt.com.

Note: In Software Synchronized mode, the time base of the ML506 is not synchronized with the rest of the model, which may cause glitches on waveforms of Analog Output modules. It is therefore not recommended to use this mode.

Direct Feedthrough	No
Discrete sample time	No
XHP support	Yes
Work offline	No

OpCtrl ML506XSG