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Software Requirements and Compatibility Charts

Recommended configuration

The RT-XSG toolbox needs the following software in order to be able to generate a programming file for the targeted FPGA:

  • Microsoft® Windows® 10
  • Xilinx®Vivado® System Suite with System Generator for DSPTM or AMD-Xilinx® Vivado ML Enterprise Edition with Vitis Model ComposerTM (refer to the tables below to see which version best suits your needs)
  • MathWorks® MATLAB® and Simulink® (refer to the tables below to see which version best suits your needs)

When selecting a combination of RT-XSG / MATLAB and Vivado version, please refer to the three tables below.

Compatibility between AMD/ XILINX® Vivado® and MathWorks® MATLAB®

The information below is derived from one of the following links:

Vivado download: https://www.xilinx.com/support/download.html .

Note: It is not a table that is showing the limitations of RT-XSG. It is rather a goal to reach with a RT-XSG revision.

   MATLAB®

Vivado®    

2017a

2017b

2018a

2018b

2019a 

2019b

2020a

2020b

2021a

2021b

2022a

2022b

2018.13,4,5

Y

Y

N2

N

N

NNNNNNN

2018.25
2018.3

Y

Y

Y

N

N

NNNNNNN

2019.1

N

N

Y

Y

Y

NNNNNNN
2019.2NNYYYYNNNNNN
2020.1NNNNYYYNNNNN
2020.2NNNNYYYYNNNN
2020.36NNNNNNNNNN
NN
2021.1NNNNNNYYYNNN
2021.2
NNNNNNYYYNNN
2022.1
NNNNNNNNYYNN
2022.2NNNNNNNN

Y

YNN
2023.1NNNNNNNNYYYN
  • Combinations supported by Xilinx® Vivado® or AMD-Xilinx® are highlighted in Yellow.
  • Please note the combinations highlighted in Red.
  • 1: 2015.3/2014b : First version of Vivado® supported by RT-XSG software component
  • 2: 2018.1/2018a : In Xilinx®’s documentation (UG973 and above reference #55830), the supported MATLAB® versions are only R2017a and R2017b. However, with System Generator 2018.1 MATLAB® Configurator, R2018a is also available. 
  • 3: For simulators using Xilinx® UltraScale+, the minimal revision is 2018.1 for supporting Aurora 8B/10B of Production revision.
  • 4 Patch is required by the user, see https://www.xilinx.com/support/answers/70908.html
  • 5 Patch is required (https://www.xilinx.com/support/answers/71410.html) by using specific RT-XSG revision with advanced parameters on Xilinx® opt_design executable: 3.3.1.711 or higher
  • 6: Revision for Versal only
  • Compatibility between OPAL-RT RT-XSG and Xilinx® Vivado® or AMD-Xilinx®
  • Support for Vivado® started with version 2015.3. Versions 2016.1 and 2016.2 are not supported.
  • PLEASE NOTE THAT THE REVISIONS 20##.#.1 are not shown because they are not supported
    • 2017.1.1, 2017.2.1, 2017.3.1, 2018.1.1, 2018.2.1, 2018.3.1, 2019.1.1, 2019.2.1,  2020.#.1, 2021.#.1, 2022.#.1, ....


Vivado®

RT-XSG

2018.1

2018.2

2018.3

2019.1

2019.2

2020.1

2020.2

2020.3

2021.1

2021.2

2022.1

2022.2

2023.1

3.3.4.807
3.3.5.810
3.3.6.811

YYYYYYYNYYYNN
3.4.0.814YYYYYYYYYYYYN
3.4.1.816YYYYYYYYYYYYN

3.5.0.817

*2 FPGA families

7-series: Y

Versal: N/A

7-series: Y

Versal: N/A

7-series: Y

Versal: N/A

7-series: Y

Versal: N/A

7-series: Y

Versal: N/A

7-series: Y

Versal: N/A

7-series: Y

Versal: N/A

7-series: Y

Versal: N/A

7-series: Y

Versal: N/A

7-series: Y

Versal: N/A

7-series: Y

Versal: N/A

7-series: Y

Versal: N2

7-series: Y

Versal: Y

  • (R): Restricted version, not globally available
  • 1: Bug with Windows 10 / Vivado 2019.2: set_param constraints.enableBinaryConstraints 0 in script BitstreamCompiler.tcl, correction made in 3.3.0+
  • Compatibility between OPAL-RT RT-XSG and MathWorks® MATLAB®
  • Vivado tool was integrated in OPAL-RT RT-XSG toolbox starting with MATLAB® 2014b.
  • 2: Bug with Vivado for bitstream generation with Versal for expansion card, therefore, support removed.



MATLAB®

RT-XSG

2017a

2017b

2018a

2018b

2019a2019b2020a2020b2021a
2021b
2022a2022b

3.3.4
3.3.5
3.3.6

YYYYYYYYYYNN
3.4.0NYYYYYYYYYNN
3.4.1NYYYYYYYYYNN
3.5.0NYYYYYYYYYYN
  • (R): Restricted version, not globally available
  • Compatibility table between OPAL-RT RT-XSG and eFPGASim/eHS is the same than the table with OPAL-RT RT-XSG and MathWorks® MATLAB®.








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