Description

This block implements a one-phase discrete phase-lock loop. It includes configurable PID controller, second-order filter and discrete rate limiter.

Mask

Inputs

S: This input must be a XFloat8_24 signal. It is the controlled signal for which the phase needs to be locked.

rst: This input must be a UFix1_0 or Bool signal. When active, the internal state variables are reset to their initial condition.

PID Params: This input must be connected to the PID Control Unpacking block. It contains the controller parameters as set from the PLL control block located in the RT-LAB simulation model.

Filter Params: This input must be connected to the Second-Order Filter Unpacking block. It contains the filter parameters as set from the PLL control block located in the RT-LAB simulation model.

Rate Limiter Params: This input must be connected to the Discrete Rate Limiter Unpacking block. It contains the rate limiter parameters as set from the PLL control block located in the RT-LAB simulation model.

Outputs

Theta: This output is the output phase of the PLL (UFix23_23).

Frequency: This output is the output frequency of the PLL (XFloat8_24).

Characteristics and limitations

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