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DC-to-AC Converters LAB 2 - 7. Circuit Description
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7.1 Converter Topology
The Three-Phase Two-Level converter is shown in figure 18:
Figure 18: Three-Phase Two-Level Inverter
The three-phase two-level inverter has six IGBT/diode switches (named as S_{1} to S_{6}) with two switches per phase.
The inverter has two inputs: (i) positive and (ii) negative terminals of the DC voltage source. It also has three outputs , and , which feed the three-phase load.
7.2 Control of the Switches & PWM Generation
The control of the switches of the first arm, that is displayed in figure 19, is explained below.
The same control is to be applied for arms two and three with a phase-shift of -120^{o} and +120^{o}, respectively.
The PWM train is generated using the method of intersection between the reference signal that is a sine-wave signal oscillating at either 60 Hz or 50 Hz, and one triangular carrier oscillating at the switching frequency.
The reason behind having one carrier (instead of two) is the fact that each arm contains two IGBTs (instead of four IGBTs, as is the case in a three-level inverter).
The comparison between the reference signal for the first arm and the carrier is illustrated in figure 20.
The switching frequency is a user-controlled parameter, varying between 900 Hz and 3000 Hz.
It is up to the user to select switching frequency values that are a multiple of 60 or 50 depending on if 60 Hz or 50 Hz is chosen as a reference frequency.
Figure 19: First Arm of the Three-Phase Two-Level Inverter
Figure 20: PWM Generation for the First Arm of the Three-Phase Two-Level Inverter
From figure 20, the student can see that switches S1 and S2 are complementary, which means that both of the switches in the same leg cannot be turned ON at the same time,
as the input DC voltage would be in short-circuit, thus violating the Kirchhoff’s voltage law (KVL).
Therefore, we have:
S_{1}+S_{2}=1
S_{3}+S_{4}=1
S_{5}+S_{6}=1
S_{1} | S_{2} | S_{5} | V_{AB} | V_{BC} | V_{CA} |
---|---|---|---|---|---|
0 | 0 | 0 | 0 | 0 | 0 |
0 | 0 | 1 | 0 | -V_{dc} | -V_{dc} |
0 | 1 | 0 | -V_{dc} | V_{dc} | 0 |
0 | 1 | 1 | -V_{dc} | 0 | V_{dc} |
1 | 0 | 0 | V_{dc} | 0 | -V_{dc} |
1 | 0 | 1 | V_{dc} | -V_{dc} | 0 |
1 | 1 | 0 | 0 | V_{dc} | -V_{dc} |
1 | 1 | 1 | 0 | 0 | 0 |
Table 11: The Switching States in a Three-Phase Two-Level Inverter
Of the eight switching states, as presented in table 11, two of them produce zero AC line voltage at the output.
In this case, the ac line currents freewheel through either the upper or lower components.
The remaining states produce no zero ac output line voltages.
In order to generate a given voltage waveform, the inverter switches from one state to another.
Thus, the resulting AC output line voltages (V_{AB}, V_{BC} and V_{CA}) consist of discrete values of voltages, which are -V_{dc, }0, and V_{dc.}
The selection of the states in order to generate the given waveform is done by a modulation technique that ensures the use of only the valid states.
7.3 Load and Filter
The load and filter are given in figure 21:
Figure 21: Load and Filter in the Three-Phase Two-Level Inverter
7.3.1 Load
The load is composed of the combination in series of (i) a constant resistance, (ii) a constant inductance and (iii) a controllable three-phase AC-source.
Therefore, the student controls the three parameters of the AC-source, namely, the amplitude, frequency, and phase-shift.
In section 9, exercises showing the impact of changing these parameters will be covered thoroughly.
7.3.1 Filter
The filter is composed of inductances in series with the load, while the capacitances are mounted in delta configuration between phases.
The filter inductance value corresponds to 10% of the load inductance.
The value of the capacitance will be computed in an exercise, later, to ensure a cut-off frequency of 600 Hz, which represents 10x the reference frequency (60Hz).
Note that the capacitors can be connected or disconnected as seen in figure 21; exercises covering this matter will be given too.
7.4 Inverter Parameters and Nameplate
The three-phase two-level parameters and its nameplate are shown in table 12.
Parameters | Value | Description |
---|---|---|
50/60 Hz | Reference frequency for PWM generation | |
0.43 Ω | Line-Neutral Resistance | |
3.02 mH | Line-Neutral Inductance | |
5000 W | Nominal Power of the inverter | |
V_{out} | [40.5 84.8] V | Line-to-line output RMS voltage of the inverter |
I_{out} | [3.5 48] A | Output RMS current of the inverter |
0.302 mH | Line-Neutral Inductance of the filter (10% of the load inductance) | |
See Ex. 9.1 | Line-Neutral Capacitance of the filter |
Table 12: Three-Phase Two-Level Inverter Parameters and Nameplate Ratings
7.5 Measurements
Three spots were considered for current, voltage and power measurements, as shown in figure 22:
- The DC bus at the input of the converter bridge.
- The AC bus at the output of the converter bridge.
- The input of the load.
Figure 22: Measurements
It is worth noticing that for the three-phase power measurements, i.e., at the second and third spot, a transformation is required first to move from line-to-line voltages to line-to-neutral voltages .
For instance, at the inverter output we have:
Then the instantaneous power is obtained as
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