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V2.19 Versal OP4815 - eHS x128 - FD Line- IMwithSAT - IO Config1

Owned by Fabien Ducat
Sept 11, 2024
3 min read

OPAL-RT TECHNOLOGIES
1751 Richardson suite 1060, Montréal QC Canada H3K 1G6
www.opal-rt.com

© 2023 OPAL-RT TECHNOLOGIES All rights reserved

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SPS WORKFLOWSCHEMATIC EDITOR WORKFLOWSCHEMATIC EDITOR WORKFLOW WITH SFUNCTION

Introduction

This firmware includes:

  • One eHS x128 Gen5 Solver
  • Two Dual Permanent Magnet Synchronous Machines (PMSM-SH) models
  • One Quad Generic Machines mode
  • Two Analog Output Mapping and Rescaling (AOMR) module


LoadIn/DataIn/DataOut mapping


LoadIn

DataIn

DataOut

1

Config eHS

Inputs eHS

eHS Averaged

2

Scenario / Rst eHS = Status

TSDO 1 - eHS 0 to 7

eHS DownSample

3

Fd Line

TSDO 2 - eHS 8 to 15

Digital In 1A - 0 to 7

4

PWM 1A -  0 to 7

TSDO 3 - eHS 16 to 23

Digital In 1A - 8 to 15

5

PWM 1A -  8 to 15

TSDO 4 - eHS 24 to 31

Digital In 1A - 16 to 23

6

PWM 1A -  16 to 23

TSDO 5 - eHS 32 to 39

Digital In 1A - 24 to 31

7

PWM 1A -  24 to 31

TSDO 6 - eHS 40 to 47

Digital In 2A - 0 to 7

8

PWM 2A -  0 to 7

TSDO 7 - eHS 48 to 55

Digital In 2A - 8 to 15

9

PWM 2A -  8 to 15

TSDO 8 - eHS 56 to 63

Digital In 2A - 16 to 23

10

PWM 2A -  16 to 23

TSDO 9 - eHS 64 to 71

Digital In 2A - 24 to 31

11

PWM 2A -  24 to 31

Digital Out 1A - SDO 0 to 7

Analog In 1C - 0 to 7

12

Config AOMR

Digital Out 1A - SDO 8 to 15

Analog In 1C - 8 to 15

13

eHS PWM 1 - eHS 0 to 7

Digital Out 1A - SDO 16 to 23

Quad Generic Machine with Saturation

14

eHS PWM 2 - eHS 8 to 15

Digital Out 1A - SDO 24 to 31

Quadrature Encoder 0

15

eHS PWM 3 - eHS 16 to 23

Digital Out 2A - SDO 0 to 7

Quadrature Encoder 1

16

eHS PWM 4 - eHS 24 to 31

Digital Out 2A - SDO 8 to 15

Quadrature Encoder 2

17

Config AIR

Digital Out 2A - SDO 16 to 23

Quadrature Encoder 3

18

Config Quad Generic Machine with Saturation

Digital Out 2A - SDO 24 to 31

Analog In 2C - 0 to 7

19


AOMR/Analog Out 1B 0 to 7

Analog In 2C - 8 to 15

20


Analog Out 1B 8 to 15

eHS Period Averaged

21


Analog Out 2B 0 to 7

eHS Period DownSample

22

Config SFP

Analog Out 2B 8 to 15

TimeOn Averaged

23

Config Lookup Table

eHS PWM 1 -  0 to 7

TimeOn DownSample

24

RMS and Power Calculation

eHS PWM 2 -  8 to 15

RMS and Power Calculation

25

Config Quadrature Encoder

eHS PWM 3 -  16 to 23


26

Config AOMR

eHS PWM 4 -  24 to 31


27


eHS SWG


28

QEI0 config



29QEI1 config

30QEI2 configConfig Quad Generic Machine with Saturation

31

QEI3 config

AOMR 2A 0 to 7


32
Quadrature Encoder
33
TSDO 10 - eHS 72 to 79
34
TSDO 11 - eHS 80 to 87
35
TSDO 12 - eHS 88 to 95
36
TSDO 13 - eHS 96 to 103
37
TSDO 14 - eHS 104 to 111
38
TSDO 15 - eHS 112 to 119
39
TSDO 16 - eHS 120 to 127
40
TSDO 17 - eHS 128 to 135
41
TSDO 18 - eHS 136 to 143
42
SFP
43
Lookup Table Config

System Overview


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Quad Generic Machine model (GM)

A total of four Induction Machines (IM) are available and configured using Generic Machine block in the eFPGAsim library.

Schematic Editor Workflow - Generic Machine block

SPS Workflow - Generic Machine block

Communication port configuration for the Quad Generic Machine (GM) block

      

Quad Generic Machine

Machine Label

IMwithSAT 1

IMwithSAT 2

IMwithSAT 3IMwithSAT 4

Data In Port Number

30

Load In Port Number

18

Data Out Port Number

13

Connectivity (Input)

The signals received could be used as external carrier for machine resolver module. 
Analog In - Slot 2A - Ch00-01

Encoder Output

Encoder outputs are sent to 
Digital Out - Slot 2B

Encoder 1Encoder 2Encoder 3Encoder 4
ACh00Ch04Ch08Ch12
BCh01Ch05Ch09Ch13
ZCh02Ch06Ch10Ch14


Power calculation module

SPS WORKFLOW SPECIFIC SCHEMATIC EDITOR WORKFLOW WITH SFUNCTION

RMS and power calculation for all circuit measurements is configured using the “Power Measurement Controller” block in the CPU model.

For more documentation on the block see : https://opal-rt.atlassian.net/wiki/spaces/PFPET/pages/65835684/CPU+Power+Measurement+Configuration+-+efs+Monitoring+cpuPowerBlock

Communication port configuration for the Power calculation block


RMS

Load In Port Number24
Data Out Port Number16

Analog Output Mapping and Rescaling module (AOMR)

AUTOMATIC AND NOT VISIBLE IN SCHEMATIC EDITOR WORKFLOW

There is one AOMR block allowing to configure all 32 analog outputs.

AOMR Master Subsystem (SM) block

Communication port configuration for the Analog Output Mapping and Rescaling (AOMR) block


AOMR - Slot 1A

AOMR - Slot 2A

Version V2
Data In Port Number1931
Load In Port Number1217

AOMR Output

Lane IndexSignal SourceDetails
0eHS OutputseHS Y01-128
1PMSM SH 1/2 AnalogOut
Dual PMSM SH Model
2PMSM SH 3/4 AnalogOut
3Generic Machine


4Data Stream from SFP #01

SFP Mapping and Communication Block

A total of 32 inputs and 32 outputs are available and configured using the SFP mapping and communication block.

Schematic Editor Workflow - SFP Mapping and Communication block


Communication port configuration for the SFP mapping and communication block


SFP - Channel 0

Data In Port Number42
Load In Port Number22

Analog In module (AI)

AI block reads signals from analog input channels on the simulator. 

Schematic Editor Workflow - OPAL-Board/AI

RT-LAB

HYPERSIM


Communication port configuration for the Analog Input (AI) block


Slot 1C

ChannelsCh00-07Ch08-15
Data Out Port Number1112

Slot 2C 

ChannelsCh00-07Ch08-15
Data Out Port Number1819

Connector Pin Assignment

Please refer to your hardware documentation

Hardware Pin assignment


Analog Out module (AO)

AO block configures analog output channels on the simulator. 

Schematic Editor Workflow - OPAL-Board/AO

RT-LAB

HYPERSIM


Communication port configuration for the Analog Output (AO) block


Slot 1B 

Slot 2B
ChannelsCh00-07Ch08-15Ch00-07Ch08-15
Data In Port Number19202122

Connector Pin Assignment

Please refer to your hardware documentation

Hardware Pin assignment


Digital In module (DI)

DI block reads signals from digital input channels on the simulator. It could be static, TSDI or PWMIn.

Schematic Editor Workflow - OPAL-Board/DI

RT-LAB

HYPERSIM


Communication port configuration for theDigital Input (DI) block


Slot 1A 

Slot 2A
ChannelsCh00-07Ch08-15Ch16-23Ch24-31Ch00-07Ch08-15Ch16-23Ch24-31
Data Out Port Number345678910

Connector Pin Assignment

Please refer to your hardware documentation

Hardware Pin assignment


Digital Out module (DO)

DO block configures digital output channels on the simulator. It could be static, TSDO or PWMOut.

Schematic Editor Workflow - OPAL-Board/DO

RT-LAB

HYPERSIM


Communication port configuration for theDigital Output (DO) block


Slot 1A 

Slot 2A 
ChannelsCh00-07Ch08-15Ch16-23Ch24-31Ch00-07Ch08-15Ch16-23Ch24-31
Data In Port Number345678910
Load In Port Number4567891011

Connector Pin Assignment

Please refer to your hardware documentation

Hardware Pin assignment

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