OPAL-RT TECHNOLOGIES
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SPS WORKFLOW SCHEMATIC EDITOR WORKFLOWSCHEMATIC EDITOR WORKFLOW WITH SFUNCTION

Introduction

This firmware includes:

One eHS x128 Gen4 Solver
One Frequency Dependent Line (FD Line)
One Quad Generic Machines model with Saturation
One Analog Output Mapping and Rescaling (AOMR) module
One Analog Input Differential Rescaling (AIR) module

LoadIn/DataIn/DataOut mapping

	LoadIn	DataIn	DataOut
1	Config eHS	Inputs eHS	eHS Averaged
2	Scenario / Rst eHS = Status	TSDO 1 - eHS 0 to 7	eHS DownSample
3	Fd Line	TSDO 2 - eHS 8 to 15	Digital In 1A - 0 to 7
4	PWM 1A - 0 to 7	TSDO 3 - eHS 16 to 23	Digital In 1A - 8 to 15
5	PWM 1A - 8 to 15	TSDO 4 - eHS 24 to 31	Digital In 1A - 16 to 23
6	PWM 1A - 16 to 23	TSDO 5 - eHS 32 to 39	Digital In 1A - 24 to 31
7	PWM 1A - 24 to 31	TSDO 6 - eHS 40 to 47	Analog In 2A - 0 to 7
8		TSDO 7 - eHS 48 to 55	Analog In 2A - 8 to 15
9		TSDO 8 - eHS 56 to 63	Quad Generic Machine with SAT
10		TSDO 9 - eHS 64 to 71	QEI 0
11		Digital Out 1A - SDO 0 to 7	QEI 1
12	Config AOMR 0	Digital Out 1A - SDO 8 to 15	RMS and Power calculation
13	eHS PWM 1 - eHS 0 to 7	Digital Out 1A - SDO 16 to 23
14	eHS PWM 2 - eHS 8 to 15	Digital Out 1A - SDO 24 to 31
15	eHS PWM 3 - eHS 16 to 23
16	eHS PWM 4 - eHS 24 to 31
17	Config AIR
18	QEI config
19	Config Quad Generic Machine with Saturation	AOMR/Analog Out 1B - 0 to 7
20	QEI config	Analog Out 1B - 8 to 15
21	RMS and power calculation	Analog Out 2B - 0 to 7
22	QEO config	Analog Out 2B - 8 to 15
23	SFP config	eHS PWM 1 - 0 to 7
24	LUT config	eHS PWM 2 - 8 to 15
25		eHS PWM 3 - 16 to 23
26		eHS PWM 4 - 24 to 31
27		eHS SWG
28		Quad Generic Machine with SAT
29		LUT
30		SFP
31		TSDO 10 - eHS 72 to 79
32		TSDO 11 - eHS 80 to 87
33		TSDO 12 - eHS 88 to 95
34		TSDO 13 - eHS 96 to 103
35		TSDO 14 - eHS 104 to 111
36		TSDO 15 - eHS 112 to 119
37		TSDO 16 - eHS 120 to 127
38		TSDO 17 - eHS 128 to 135
39		TSDO 18 - eHS 136 to 143
40		QEO

System Overview

Extensive I/O compatibility (Polymorphism)

Listed cards are compatible at the same location

Digital In/Out Mezzanine
Compatible Mezzanine Modules
OP5369

Analog Out Mezzanine
Compatible Mezzanine Modules
OP5330-3 16 Aout
OP5330-1 16 Aout

Analog In Mezzanine
Compatible Mezzanine Modules
OP5340-1 16 Ain
OP5340-2 16 Ain

Expansion Mezzanine
Compatible Mezzanine Modules
OP5969-1 DIN/DOUT RS422 5V
OP5969-2 DIN/DOUT FIBER OPTIC

eHS solver

SPS WORKFLOW SPECIFIC

Connectivity

SPS WORKFLOW SPECIFIC

Source Type	Source Index	Source Name	Details
Input	0	CPU Input
	1	eHS Analog In	Slot 2A - Ch00-15
	2	Quad Generic Machine	IM1 Stator Ia/IM1 Stator Ib/IM1 Rotor Ia/IM1 Rotor Ib
			IM2 Stator Ia/IM2 Stator Ib/IM2 Rotor Ia/IM2 Rotor Ib
			IM3 Stator Ia/IM3 Stator Ib/IM3 Rotor Ia/IM3 Rotor Ib
			IM4 Stator Ia/IM4 Stator Ib/IM4 Rotor Ia/IM4 Rotor Ib
	3	Sine Wave Generator
	4	Look Up Table
	5	Data Stream from SFP #00
	6	Frequency Dependent Line
Gate	0	CPU Gating Signal
	1	PWM
	2	Digital Input	Slot 1A - Ch00-31

SPS WORKFLOW SPECIFIC

To contextualize the Input and Gate Configuration table with this firmware configuration, the eHS firmware config tab must be configured with the following custom input source enumeration:

{'CPU Model',0,128;'Analog In',1,16;'GM',2,16;'Sine Wave Generator',3,32;}

And this custom gate sources enumeration:

{'CPU Model',0,72;'Digital Inputs',2,64;'PWM',1,32}

Quad Generic Machine model (GM)

A total of four Induction Machines (IM) are available and configured using Generic Machine block in the eFPGAsim library.

Schematic Editor Workflow - Generic Machine block

SPS Workflow - Generic Machine block

Communication port configuration for the Quad Generic Machine (GM) block

	Quad Generic Machine
Machine Label	IMwithSAT 1	IMwithSAT 2	IMwithSAT 3	IMwithSAT 4
Data In Port Number	28
Load In Port Number	19
Data Out Port Number	9

Connectivity (Input)

The signals received could be used as external carrier for machine resolver module.

Analog In - Slot 2A - Ch00-01

Encoder Output

Encoder outputs are sent to

Digital Out - Slot 2B

	Encoder 1	Encoder 2
A	Ch00	Ch04
B	Ch01	Ch05
Z	Ch02	Ch06

Power calculation module

SPS WORKFLOW SPECIFIC SCHEMATIC EDITOR WORKFLOW WITH SFUNCTION

RMS and power calculation for all circuit measurements is configured using the “Power Measurement Controller” block in the CPU model.

For more documentation on the block see : https://opal-rt.atlassian.net/wiki/spaces/PFPET/pages/65835684/CPU+Power+Measurement+Configuration+-+efs+Monitoring+cpuPowerBlock

Communication port configuration for the Power calculation block

	RMS
Load In Port Number	21
Data Out Port Number	12

Analog Output Mapping and Rescaling module (AOMR)

AUTOMATIC AND NOT VISIBLE IN SCHEMATIC EDITOR WORKFLOW

There is one AOMR block allowing to configure all 32 analog outputs.

AOMR Master Subsystem (SM) block

Communication port configuration for the Analog Output Mapping and Rescaling (AOMR) block

	AOMR - Slot 2B
Version	V2
Data In Port Number	19
Load In Port Number	12

Analog Input Differential Rescaling module (AIR)

AUTOMATIC AND NOT VISIBLE IN SCHEMATIC EDITOR WORKFLOW

AIR block configures analog inputs for eHS.

AIR block

Communication port configuration for the Analog Input Differential Rescaling (AIR) block

	AIR -Slot 2A
Channels	Ch00-15
Load In Port Number	17

SFP Mapping and Communication Block

A total of 32 inputs and 32 outputs are available and configured using the SFP mapping and communication block.

Schematic Editor Workflow - SFP Mapping and Communication block

Communication port configuration for the SFP mapping and communication block

	SFP - Channel 0
Data In Port Number	30
Load In Port Number	23

Analog In module (AI)

AI block reads signals from analog input channels on the simulator.

SPS Workflow - AI block

Schematic Editor Workflow - OPAL-Board/DO

RT-LAB

HYPERSIM

Communication port configuration for the Analog Input (AI) block

	Slot 2A
Channels	Ch00-07	Ch08-15
Data Out Port Number	7	8

Connector Pin Assignment

Please refer to your hardware documentation

Hardware Pin assignment

Analog Out module (AO)

AO block configures analog output channels on the simulator.

SPS Workflow - AO block

Schematic Editor Workflow - OPAL-Board/DO

RT-LAB

HYPERSIM

Communication port configuration for the Analog Output (AO) block

	Slot 1B		Slot 2B
Channels	Ch00-07	Ch08-15	Ch00-07	Ch08-15
Data In Port Number	19	20	21	22

Connector Pin Assignment

Please refer to your hardware documentation

Hardware Pin assignment

Digital In module (DI)

DI block reads signals from digital input channels on the simulator. It could be static, TSDI or PWMIn.

SPS Workflow - DI block

Schematic Editor Workflow - OPAL-Board/DO

RT-LAB

HYPERSIM

Communication port configuration for the Digital Input (DI) block

	Slot 1A
Channels	Ch00-07	Ch08-15	Ch16-23	Ch24-31
Data Out Port Number	3	4	5	6

Connector Pin Assignment

Please refer to your hardware documentation

Hardware Pin assignment

Digital Out module (DO)

DO block configures digital output channels on the simulator. It could be static, TSDO or PWMOut.

SPS Workflow - DO block

Schematic Editor Workflow - OPAL-Board/DO

RT-LAB

HYPERSIM

Communication port configuration for the Digital Output (DO) block

	Slot 1A
Channels	Ch00-07	Ch08-15	Ch16-23	Ch24-31
Data In Port Number	11	12	13	14
Load In Port Number	4	5	6	7

Connector Pin Assignment

Please refer to your hardware documentation

Hardware Pin assignment