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V2.14 Virtex-7 VC707 - eHS x128 - Gen5 - IO Config1

OPAL-RT TECHNOLOGIES
1751 Richardson suite 1060, Montréal QC Canada H3K 1G6
www.opal-rt.com

© 2023 OPAL-RT TECHNOLOGIES All rights reserved

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SCHEMATIC EDITOR WORKFLOW

Introduction

This firmware includes:

  • One eHS x128 Gen5 Solver
  • One Analog Output Mapping and Rescaling (AOMR) module
  • One Analog Input Differential Rescaling (AIR) module
  • One Saturable Transformer (satXFO) module


LoadIn/DataIn/DataOut mapping

Port

LoadIn

DataIn

DataOut

1

Config eHS

Inputs eHS

eHS Averaged

2

Scenario / Rst eHS = Status

TSDO 1 - eHS 0 to 7

eHS DownSample

3


TSDO 2 - eHS 8 to 15

Digital In 2A - 0 to 7

4

PWM 2B -  0 to 7

TSDO 3 - eHS 16 to 23

Digital In 2A - 8 to 15

5

PWM 2B -  8 to 15

TSDO 4 - eHS 24 to 31

Digital In 2A - 16 to 23

6

PWM 2B -  16 to 23

TSDO 5 - eHS 32 to 39

Digital In 2A - 24 to 31

7

PWM 2B -  24 to 31

TSDO 6 - eHS 40 to 47

Digital In 4A - 0 to 7

8

PWM 4B -  0 to 7

TSDO 7 - eHS 48 to 55

Digital In 4A - 8 to 15

9

PWM 4B -  8 to 15

TSDO 8 - eHS 56 to 63

Digital In 4A - 16 to 23

10

PWM 4B -  16 to 23

TSDO 9 - eHS 64 to 71

Digital In 4A - 24 to 31

11

PWM 4B -  24 to 31

Digital Out 2B - SDO 0 to 7

Analog In 1B - 0 to 7

12

Config AOMR

Digital Out 2B - SDO 8 to 15

Analog In 1B - 8 to 15

13

eHS PWM 1 - eHS 24 to 31

Digital Out 2B - SDO 16 to 23

PMSM VDQ 2

14

eHS PWM 2 - eHS 0 to 7

Digital Out 2B - SDO 24 to 31

PMSM VDQ 2

15

eHS PWM 3 - eHS 8 to 15

Digital Out 4B - SDO 0 to 7

eHS Period Averaged

16

eHS PWM 4 - eHS 16 to 23

Digital Out 4B - SDO 8 to 15

eHS Period DownSample

17

Config AIR

Digital Out 4B - SDO 16 to 23

TimeOn Averaged

18

Config PMSM VDQ 1

Digital Out 4B - SDO 24 to 31

TimeOn DownSample

19

Config PMSM VDQ 2

AOMR/Analog Out 1A -  0 to 7

RMS and Power calculation

20


Analog Out 1A -  8 to 15


21


Analog Out 3A -  0 to 7


22

SFP

Analog Out 3 -  8 to 15


23

Lookup table

eHS PWM 1 -  0 to 7


24

Config AOMR

eHS PWM 2 -  8 to 15


25

RMS and Power calculation

eHS PWM 3 -  16 to 23


26


eHS PWM 4 -  24 to 31


27


eHS SWG


28


PMSM VDQ 1


29
PMSM VDQ 2

30




31
Analog Out 3B -  0 to 7
32
Analog Out 3B -  8 to 15
33


34
SFP
35
Lookup Table Config

System Overview

Extensive I/O compatibility (Polymorphism)

Listed cards are compatible at the same location (More details)





SFP Mapping and Communication Block

A total of 32 inputs and 32 outputs are available and configured using the SFP mapping and communication block.

Schematic Editor Workflow - SFP Mapping and Communication block


Communication port configuration for the SFP mapping and communication block


SFP - Channel 0

Data In Port Number34
Load In Port Number22

Analog In module (AI)

AI block reads signals from analog input channels on the simulator. 

Schematic Editor Workflow - OPAL-Board/DO

RT-LAB

HYPERSIM


Connector Pin Assignment

Please refer to your hardware documentation

Hardware Pin assignment


Analog Out module (AO)

AO block configures analog output channels on the simulator. 

Schematic Editor Workflow - OPAL-Board/DO

RT-LAB

HYPERSIM


Connector Pin Assignment

Please refer to your hardware documentation

Hardware Pin assignment


Digital In module (DI)

DI block reads signals from digital input channels on the simulator. It could be static, TSDI or PWMIn.

Schematic Editor Workflow - OPAL-Board/DO

RT-LAB

HYPERSIM


Connector Pin Assignment

Please refer to your hardware documentation

Hardware Pin assignment


Digital Out module (DO)

DO block configures digital output channels on the simulator. It could be static, TSDO or PWMOut.

Schematic Editor Workflow - OPAL-Board/DO

RT-LAB

HYPERSIM


Connector Pin Assignment

Please refer to your hardware documentation

Hardware Pin assignment

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