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V2.14 Virtex-7 VC707 - eHS x128 - PMSM - IM - SRM - IO Config1
OPAL-RT TECHNOLOGIES
1751 Richardson suite 1060, Montréal QC Canada H3K 1G6
www.opal-rt.com
© 2023 OPAL-RT TECHNOLOGIES All rights reserved
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SPS WORKFLOW
Introduction
This firmware includes:
- One eHS x128 Gen4 Solver
- Two Dual Permanent Magnet Synchronous Machines (PMSM-VDQ) models
- Four Asynchronous Induction Machine (IM) models
- Two Five-phase Switched Reluctance Machine (SRM) models
- Two Resolver and Encoder models
- Two Analog Output Mapping and Rescaling (AOMR) modules
LoadIn/DataIn/DataOut mapping
LoadIn | DataIn | DataOut | |
1 | Config eHS | Inputs eHS | eHS Averaged |
2 | Scenario / Rst eHS = Status | TSDO 1 - eHS 0 to 7 | eHS DownSample |
3 | TSDO 2 - eHS 8 to 15 | Digital In 2A - 0 to 7 | |
4 | PWM 2B - 0 to 7 | TSDO 3 - eHS 16 to 23 | Digital In 2A - 8 to 15 |
5 | PWM 2B - 8 to 15 | TSDO 4 - eHS 24 to 31 | Digital In 2A - 16 to 23 |
6 | PWM 2B - 16 to 23 | TSDO 5 - eHS 32 to 39 | Digital In 2A - 24 to31 |
7 | PWM 2B - 24 to 31 | TSDO 6 - eHS 40 to 47 | Digital In 4A - 0 to 7 |
8 | PWM 4B - 0 to 7 | TSDO 7 - eHS 48 to 55 | Digital In 4A - 8 to 15 |
9 | PWM 4B - 8 to 15 | TSDO 8 - eHS 56 to 63 | Digital In 4A - 16 to 23 |
10 | PWM 4B - 16 to 23 | eHS SWG | Digital In 4A - 24 to 31 |
11 | PWM 4B - 24 to 31 | PMSM VDQ 1/2 | Analog In 1B - 0 to 7 |
12 | Config AOMR - Analog Out 1A/3A | PMSM VDQ 3/4 | Analog In 1B - 8 to 15 |
13 | Config AOMR - Analog Out 3B | IM1 | PMSM VDQ 1/2 |
14 | Config MechMux | IM1 Mtx | PMSM VDQ 3/4 |
15 | Config Resolver/Encoder 1/2 Offset | IM2 | IM1 |
16 | Config Resolver/Encoder 1/2 | IM2 Mtx | IM2 |
17 | Config Resolver/Encoder 1/2 PhaseShift | IM3 | IM3 |
18 | Config Resolver/Encoder 3/4 Offset | IM3 Mtx | IM4 |
19 | Config PMSM VDQ 1/2 | IM4 | SRM1 |
20 | Config PMSM VDQ 3/4 | IM4 Mtx | SRM2 |
21 | Config IM1 | SRM1 | Resolver/Encoder 1/2 |
22 | Config IM2 | SRM2 | Resolver/Encoder 3/4 |
23 | Config IM3 | Digital Out 2B - SDO 0 to 7 | RT-XSG Scope |
24 | Config IM4 | Digital Out 2B - SDO 8 to 15 | Encoder 1/2 Input |
25 | Config SRM1 | Digital Out 2B - SDO 16 to 23 | Encoder 3/4 Input |
26 | Config SRM2 | Digital Out 2B - SDO 24 to 31 | |
27 | Config eHS to Machines Mapping | Digital Out 4B - SDO 0 to 7 | |
28 | Config Resolver/Encoder 3/4 | Digital Out 4B - SDO 8 to 15 | |
29 | Config Resolver/Encoder 3/4 PhaseShift | Digital Out 4B - SDO 16 to 23 | |
30 | Config RT-XSG Scope | Digital Out 4B - SDO 24 to 31 | |
31 | Config Encoder 1/2 Input on Digital Input 2A | AOMR - Analog Out 1A/3A | |
32 | Config Encoder 3/4 Input on Digital Input 2A | AOMR - Analog Out 3B |
System Overview
Extensive I/O compatibility (Polymorphism)
Listed cards are compatible at the same location (More details)
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eHS solver
SPS WORKFLOW SPECIFIC
Connectivity
SPS WORKFLOW SPECIFIC
Source Type | Source Index | Source Name | Details |
---|---|---|---|
Input | 0 | CPU Input | |
1 | N/A | ||
2 | PMSM VDQ 1/2 | PMSM1 Ia/PMSM1 Ib | |
PMSM2 Ia/PMSM2 Ib | |||
PMSM3 Ia/PMSM3 Ib | |||
PMSM4 Ia/PMSM4 Ib | |||
3 | Sine Wave Generator | ||
4 | Induction Machine | IM1 Stator Ia/IM1 Stator Ib/IM1 Rotor Ia/IM1 Rotor Ib | |
IM2 Stator Ia/IM2 Stator Ib/IM2 Rotor Ia/IM2 Rotor Ib | |||
IM3 Stator Ia/IM3 Stator Ib/IM3 Rotor Ia/IM3 Rotor Ib | |||
IM4 Stator Ia/IM4 Stator Ib/IM4 Rotor Ia/IM4 Rotor Ib | |||
5 | Switched Relutance Machine | SRM1 Ia/SRM1 Ib/SRM1 Ic/SRM1 Id/SRM1 Ie | |
SRM2 Ia/SRM2 Ib/SRM2 Ic/SRM2 Id/SRM2 Ie | |||
Gate | 0 | CPU Gating Signal | |
1 | PWM | ||
2 | Digital Input | Slot 2A - Ch00-31/Slot 4A - Ch00-31 |
SPS WORKFLOW SPECIFIC
To contextualize the Input and Gate Configuration table with this firmware configuration, the eHS firmware config tab must be configured with the following custom input source enumeration:
{'CPU Model',0,128;'Sine Wave Generator',3,32;'PMSM',2,8;'IM',4,16;'SRM',5,10}
And this custom gate sources enumeration:
{'CPU Model',0,64;'Digital Inputs',2,64;'PWM',1,32}
Permanent Magnet Synchronous Machine (PMSM - VDQ) model
SPS WORKFLOW SPECIFIC
A total of two PMSM (VDQ) are available and are configured using the Dual PMSM VDQ block in the CPU model. The following communication ports need to be configured.
SPS Workflow - Dual PMSM Motors VDQ
Communication port configuration for the Dual PMSM (VDQ) block
| Dual PMSM Motors VDQ 1 | |
Machine Label | PMSM 1 | PMSM 2 |
Data In Port Number | 11 | |
Load In Port Number | 19 | |
Data Out Port Number | 13 |
| Dual PMSM Motors VDQ 2 | |
Machine Label | PMSM 3 | PMSM 4 |
Data In Port Number | 12 | |
Load In Port Number | 20 | |
Data Out Port Number | 14 |
Induction Machine (IM) model
SPS WORKFLOW SPECIFIC
One IM is available and configured using the Induction Machine block in the CPU model. The following communication ports need to be configured.
SPS Workflow - Induction Machine
Communication port configuration for the Induction Machine (IM) block
IM 1 | IM 2 | IM 3 | IM 4 | |
---|---|---|---|---|
Data In Port Number | 13 | 15 | 17 | 19 |
Data In Mtx Port Number | 14 | 16 | 18 | 20 |
Load In Port Number | 21 | 22 | 23 | 24 |
Data Out Port Number | 15 | 16 | 17 | 18 |
Switched Reluctance Motor (SRM) model
SPS WORKFLOW SPECIFIC
One switched reluctance machine is available and are configured using the “Switch Reluctance Motor” block in the CPU model. The following communication ports need to be configured.
SPS Workflow - Switched Relutance Motor
Communication port configuration for the Switched Reluctance Machine (SRM) block
SRM 1 | SRM 2 | |
---|---|---|
Data In Port Number | 21 | 22 |
Load In Port Number | 25 | 26 |
Data Out Port Number | 19 | 20 |
Resolver and Encoder Outputs
SPS WORKFLOW SPECIFIC
There are resolver/encoder outputs that can be assigned to any of the motors. Resolver excitation can be configured either as internal or external.
The cpuhilsensors_lib/DualAngleSensors_wfaults Simulink block in the figure below is used for configuration of the Resolver/Encoder Out feature. Please refer to the block help and the User Guide for eHS & Machine package for further information.
SPS Workflow - Resolver/Encoder out configuration block
The mapping of the Resolver/Encoder out is achieved with the mapping block below. A total of 5 machine angles can be mapped to any of the 2 Resolvers/Encoders. Follows the correct configuration of the CPU block.
SPS Workflow - Resolver/Encoder mapping block
SPS Workflow - Resolver/Encoder mapping block configuration
Communication port configuration for the Resolver and Encoder block
Resolver/Encoder 1/2 | Resolver/Encoder 3/4 | |
---|---|---|
Load In Port Number | 16 | 28 |
Offset Load In Port Number | 15 | 18 |
PhaseShift Load In Port Number | 17 | 29 |
Data Out Port Number | 21 | 22 |
Connectivity (Input)
Analog In - Slot 1B - Ch00-03
Communication port configuration for the Resolver and Encoder Mapping block
Resolver/Encoder 1/2/3/4 | |
---|---|
Load In Port Number | 14 |
Analog Output Mapping and Rescaling module (AOMR)
AUTOMATIC AND NOT VISIBLE IN SCHEMATIC EDITOR WORKFLOW
There is one AOMR block allowing to configure all 32 analog outputs.
AOMR Master Subsystem (SM) block
Communication port configuration for the Analog Output Mapping and Rescaling (AOMR) block
AOMR - Slot 1A /3A | AOMR - Slot 3B | |
---|---|---|
Verison | V1 | |
Data In Port Number | 31 | 32 |
Load In Port Number | 12 | 13 |
AOMR Output
Index | Signal Name |
---|---|
0 | Resolver 1 Sine |
1 | Resolver 1 Cosine |
2 | Resolver 2 Sine |
3 | Resolver 2 Cosine |
4 | Resolver 3 Sine |
5 | Resolver 3 Cosine |
6 | Resolver 3 Sine |
7 | Resolver 4 Cosine |
8 .. 47 | Not Used |
48 .. 127 | User Defined |
128 .. 255 | eHS Y001 to Y128 |
Analog In module (AI)
AI block reads signals from analog input channels on the simulator.
SPS Workflow - AI block
Communication port configuration for the Analog Input (AI) block
Slot 1B | ||
---|---|---|
Channels | Ch00-07 | Ch08-15 |
Data Out Port Number | 11 | 12 |
Connector Pin Assignment
Please refer to your hardware documentation
Digital In module (DI)
DI block reads signals from digital input channels on the simulator. It could be static, TSDI or PWMIn.
SPS Workflow - DI block
Communication port configuration for the Digital Input (DI) block
Slot 2A | Slot 4A | |||||||
---|---|---|---|---|---|---|---|---|
Channels | Ch00-07 | Ch08-15 | Ch16-23 | Ch24-31 | Ch00-07 | Ch08-15 | Ch16-23 | Ch24-31 |
Data Out Port Number | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 |
Connector Pin Assignment
Please refer to your hardware documentation
Digital Out module (DO)
DO block configures digital output channels on the simulator. It could be static, TSDO or PWMOut.
SPS Workflow - DO block
Communication port configuration for the Digital Output (DO) block
Slot 2B | Slot 4B | |||||||
---|---|---|---|---|---|---|---|---|
Channels | Ch00-07 | Ch08-15 | Ch16-23 | Ch24-31 | Ch00-07 | Ch08-15 | Ch16-23 | Ch24-31 |
Data In Port Number | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 |
Load In Port Number | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 |
Connector Pin Assignment
Please refer to your hardware documentation
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