Objective:

This page attempts to inform the user of the latency involved in a firmware containing eHS and Motor, from the perspective of an arriving Digital Input and ending at a consequent analog output being available at the driving DAC.

It will detail eHS latency between a gate pulse and consequent output occurrence in AOMR.

Variable Delay eHS can be explained by:

1. When the DIN transition takes place, eHS may already be in a computation step. Maximum Delay Value = Ts_eHS

2. When AOMR sync takes place, eHS may not have computed new outputs based on a DIN transition. Maximum Delay Value = AOMR Sync Period

Timing Diagrams to understand Variable Delay eHS:

This section is a pictorial representation of the timing analysis of different signals. Some optimization delay clock ticks have been omitted for situation clarity.

Please bear in mind that the “0” Data span is not according to timescale and multiple “Data” words for eHS_OUT can be present.

General Situation

Open

Min Latency Situation

Open

1. eHS begins a new computation step 2 clock ticks after the DIN transition. Hence, it registers the transition already.

2. After 2*Ts_eHS, data corresponding to the DIN transition is available.

3. AOMR syncs one clock cycle before the “Last” word of eHS_OUT Data packet.

Max Latency Situation

1. eHS begins its computation step in the same clock cycle as the DIN transition.

2. We need to wait an extra Ts_eHS for the transition to be registered.

3. AOMR syncs just before the end of the third eHS_OUT data packet. This means it takes data from the second eHS_OUT Data packet, but the DIN transition data is available in the third packet.

4. A waiting period of AOMR sync period is needed for the next AOMR Sync, for the third data packet to be available at the Analog Output.

Variable Delay Motor can be explained by:

1. When the DIN transition takes place, eHS may already be in a computation step. Maximum Delay Value = Ts_eHS

2. When eHS Data due to DIN transition is available, Motor Solver might already be in a computation step. Maximum Delay Value = Ts_Motor

3. When AOMR sync takes place, Motor may not have computed new outputs based on the eHS Data. Maximum Delay Value = AOMR Sync Period

Timing Diagrams to understand Variable Delay Motor:

This section is a pictorial representation of the timing analysis of different signals. Some optimization delay clock ticks have been omitted for situation clarity.

Please bear in mind that the “0” Data span is not according to timescale and multiple “Data” words for eHS_OUT and Motor_OUT can be present.

General Situation

Min Latency Situation

1. eHS begins a new computation step 2 clock ticks after the DIN transition. Hence, it registers the transition already.

2. After 2*Ts_eHS, data corresponding to the DIN transition is available.

3. Motor begins its new computation step immediately after DIN transition data is made available by eHS.

4. AOMR syncs one clock cycle before the “Last” word of Motor_OUT Data packet.

Max Latency Situation

1. eHS begins its computation step in the same clock cycle as the DIN transition.

2. We need to wait an extra Ts_eHS for the transition to be registered.

3. Motor begins its new computation step immediately before the DIN transition data is made available by eHS. We need to wait an extra Ts_Motor for the transition to be registered.

4. AOMR syncs just before the end of the second Motor_OUT data packet. This means it takes data from the first Motor_OUT Data packet, but the DIN transition data is available in the second packet.

5. A waiting period of AOMR sync period is needed for the next AOMR Sync, for the second data packet to be available at the Analog Output.